| Effective exploitation of a zero overhead loop buffer |
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Language, Compiler and Tool Support for Embedded Systems
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Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
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Atlanta, Georgia, United States
Pages: 10 - 19
Year of Publication: 1999
ISBN:1-58113-136-4
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Authors
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Gang-Ryung Uh
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Lucent Technologies, Allentown, PA
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Yuhong Wang
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Department of Computer Science, Florida State University, Tallahassee, FL
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David Whalley
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Department of Computer Science, Florida State University, Tallahassee, FL
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Sanjay Jinturkar
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Lucent Technologies, Allentown, PA
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Chris Burns
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Lucent Technologies, Allentown, PA
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Vincent Cao
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Lucent Technologies, Allentown, PA
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Downloads (6 Weeks): 4, Downloads (12 Months): 34, Citation Count: 4
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ABSTRACT
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequence of instructions that will be executed a specified number of times. Unlike techniques such as loop unrolling, a loop buffer is a hardware technique that can be used to minimize loop overhead without the penalty of increasing code size. In addition, a ZOLB also requires relatively little space and power, which are both important considerations for most DSP applications. This paper describes strategies for generating code to effectively use a ZOLB. The authors have found that many common improving transformations used by optimizing compilers to improve code on conventional architectures are shown (1) to allow more loops to be placed in a ZOLB and (2) to further reduce loop overhead of the loops placed in a ZOLB. The results given in this paper demonstrate that this architectural feature can often be exploited with substantial improvements in execution time and slight reductions in code size.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Lucent Technologies, DSP16000 Digital Signal Processor Core Information Manual, 1997.
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Lucent Technologies, DSP16000 C Compiler User Guide, 1997.
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Lucent Technologies, DSP16000 Digital Signal Processor Core instruction Set Manual, 1997.
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Yuhong Wang, Interprocedural Optimizations for Embedded Systems, Masters Project, Florida State University, Tallahassee, FL (1999).
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David Whalley, DSP16000 C Optimizer Overview and Rationale, Lucent Technologies, Allentown, PA (July, 1998).
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Lucent Technologies, DSP16000 LuxWorks Debugger, 1997.
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Lucent Technologies, DSP16000 Assembly Language User Guide, 1997.
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CITED BY 4
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Gang-Ryung Uh , Yuhong Wang , David Whalley , Sanjay Jinturkar , Yunheung Paek , Vincent Cao , Chris Burns, Compiler transformations for effectively exploiting a zero overhead loop buffer, Software—Practice & Experience, v.35 n.4, p.393-412, 10 April 2005
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