Systematic and optimized layout of MOS cells

ABSTRACT

The logical synthesis methods are dependant technology and must be strongly connected to the topological design. We present here a logical and topological synthesis method for complex MOS cells leading to a systematic, optimized and easy to interconnect layout.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout; Simulation

General Terms:
Design, Measurement, Performance, Theory