Timing influenced layout design

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Timing influenced layout design

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 22nd ACM/IEEE conference on Design automation table of contents

Las Vegas, Nevada, United States

Pages: 124 - 130

Year of Publication: 1985

ISBN:0-8186-0635-5

Authors

Michael Burstein	Tangent Systems, 2840 San Tomas Expressway, Santa Clara, CA and IBM T. J. Watson Research Center, Yorktown Heights, New York
Mary N. Youssef	IBM Corporation, East Fishkill, Hopewell Junction, New York

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 37

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abstract references cited by index terms collaborative colleagues peer to peer

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ABSTRACT

We present a new approach to the automatic layout design for VLSI chips which incorporates timing information to influence the placement and wiring processes. This approach is an extension of the hierarchical layout method, in which placement and wiring are performed simultaneously [1]. We add a third phase of timing to the hierarchy, without affecting the computational complexity of the basic algorithm. Prior to the physical design, timing analysis is performed using statistical estimates for the unknown parameters; namely the lengths of interconnecting wires. The output of this analysis includes a measure for each net that indicates the degree of its contribution to the timing problem. This set of measures is used to bias the placement at the highest level of the hierarchy. Since wiring is performed after each level of partitioning, lengths of interconnecting nets among the partitions become available. These data are used to update the timing information that bias the design. Preliminary results show that, while delays due to interconnections are reduced, wireability of the chip does not deteriorate.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Burstein M., S. J. Hong and R. Pelavin, "Hierarchical VLSI Layout: Simultaneous Placement and Wiring of Gate Arrays," Proc. IFIP VLSI-83, Trondheim, August 1983.
	2	Wolf P. K., Sr. et al, "Power/Tilning: Optimization and Layout Techniques for LSI Chips," Design Automation and Fault Tolerant Computing, 1978.
	3	A. E. Dunlop , V. D. Agrawal , D. N. Deutsch , M. F. Jukl , P. Kozak , M. Wiesel, Chip layout optimization using critical path weighting, Proceedings of the 21st conference on Design automation, p.133-136, June 25-27, 1984, Albuquerque, New Mexico, United States
	4	Hitchcock, R. Sr., G. Smith, D. Cheng, "Timing Analysis of Computer Hardware," IBM Journal of Research and Development, Vol. 26, NO. 1, 1982.
	5	Kernighan, B. W. and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," Bell System Technical Journal, Vol. 49, 1982.
	6	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	7	Burstein M. and Pelavin, R., "Hier~trchical Wire Routing," IEEE Trans. on Computer-Aided Design 9f Integrated Data and Systems," Vol. CAD-2, No.4, 1983.
	8	Burstein M. and Pelavila, R., "Hierarchical Wire of Gate-Array VLSI Chips", Proe. ECCTD'83 (6-th European Conf. Circuit Theory and Design), Stuttgart, Germany, 1983.

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	William Swartz , Carl Sechen, Timing driven placement for large standard cell circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.211-215, June 12-16, 1995, San Francisco, California, United States
	Srilata Raman , C. L. Liu , Larry G. Jones, A delay driven FPGA placement algorithm, Proceedings of the conference on European design automation, p.277-282, September 19-23, 1994, Grenoble, France
	R.-B. Lin , E. Shragowitz, Fuzzy logic approach to placement problem, Proceedings of the 29th ACM/IEEE conference on Design automation, p.153-158, June 08-12, 1992, Anaheim, California, United States
	Ren-Song Tsay , Juergen Koehl, An analytic net weighting approach for performance optimization in circuit placement, Proceedings of the 28th conference on ACM/IEEE design automation, p.620-625, June 17-22, 1991, San Francisco, California, United States
	Chao-Yang Yeh , Malgorzata Marek-Sadowska, Sequential delay budgeting with interconnect prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1028-1037, October 2004
	M. A. B. Jackson , E. S. Kuh, Performance-driven placement of cell based IC's, Proceedings of the 26th ACM/IEEE conference on Design automation, p.370-375, June 25-28, 1989, Las Vegas, Nevada, United States
	Ichiang Lin , David H. C. Du, Performance-driven constructive placement, Proceedings of the 27th ACM/IEEE conference on Design automation, p.103-106, June 24-27, 1990, Orlando, Florida, United States
	Michael Hutton , Khosrow Adibsamii , Andrew Leaver, Adaptive delay estimation for partitioning-driven PLD placement, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.60-63, February 2003
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	Qinghua Liu , Bo Hu , Malgorzata Marek-Sadowska, Wire length prediction in constraint driven placement, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
	Wen-Ben Jone , Chen-Liang Fang, Timing optimization by gate resizing and critical path identification, Proceedings of the 30th international conference on Design automation, p.135-140, June 14-18, 1993, Dallas, Texas, United States
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	J. Garbers , B. Korte , H. J. Prömel , E. Schwietzke , A. Steger, VLSI: placement based on routing and timing information, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
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	H. Chang , E. Shragowitz , J. Liu , H. Youssef , B. Lu , S. Sutanthavibul, Net criticality revisited: an effective method to improve timing in physical design, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
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