Johannes de Fine Licht
Michaela Blott
Torsten Hoefler
Abstract
Massive spatial parallelism at low energy gives FPGAs the potential to be core components in large scale high performance computing (HPC) systems. In this paper we present four major design steps that harness high-level synthesis (HLS) to implement scalable spatial FPGA algorithms. To aid productivity, we introduce the open source library hlslib to complement HLS. We evaluate kernels designed with our approach on an FPGA accelerator board, demonstrating high performance and board utilization with enhanced programmer productivity. By following our guidelines, programmers can use HLS to develop efficient parallel algorithms for FPGA, scaling their implementations with increased resources on future hardware.
- Uday Bondhugula, Vinayaka Bandishti, and Irshad Pananilath. 2017. Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations. TPDS 28, 5 (May 2017), 1285--1298. Google Scholar
Digital Library
- Haohuan Fu and Robert G. Clapp. 2011. Eliminating the Memory Bottleneck: An FPGA-based Solution for 3D Reverse Time Migration. Proceedings of FPGA'11, 65--74. Google ScholarDigital Library
- Xinyu Niu, Jose G. F. Coutinho, Yu Wang, and Wayne Luk. 2013. Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters. Proceedings of FPT'13.Google ScholarCross Ref
- Nirmal Prajapati, Waruna Ranasinghe, Sanjay Rajopadhye, et al. 2017. Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU Stencils. Proceedings of PPoPP'17. Google ScholarDigital Library
- Kentaro Sano, Yoshiaki Hatsuda, and Satoru Yamamoto. 2014. Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory Bandwidth. TPDS 25, 3 (March 2014), 695--705. Google ScholarDigital Library
- Hasitha M. Waidyasooriya, Yasuhiro Takei, et al. 2017. OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology. TPDS 28, 5 (May 2017), 1390--1402. Google ScholarDigital Library
Index Terms
- Designing scalable FPGA architectures using high-level synthesis
Recommendations
Designing scalable FPGA architectures using high-level synthesis
PPoPP '18: Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel ProgrammingMassive spatial parallelism at low energy gives FPGAs the potential to be core components in large scale high performance computing (HPC) systems. In this paper we present four major design steps that harness high-level synthesis (HLS) to implement ...
Bit-level optimization for high-level synthesis and FPGA-based acceleration
FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arraysAutomated hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level programming languages, such as C/C++, the description of bitwise access ...
From software to accelerators with LegUp high-level synthesis
CASES '13: Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded SystemsEmbedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source high-level ...
Comments