ABSTRACT
Field Programmable Gate Arrays (FPGAs) are being used to provide fast Internet Protocol (IP) packet routing and advanced queuing in a highly scalable network switch. A new module, called the Field-programmable Port Extender (FPX), is being built to augment the Washington University Gigabit Switch (WUGS) with reprogrammable logic.
FPX modules reside at the edge of the WUGS switching fabric. Physically, the module is inserted between an optical line card and the WUGS gigabit switch back-plane. The hardware used for this project allows ports of the switch populated with an FPX to operate at rates up to 2.4 Gigabits/second. The aggregate throughput of the system scales with the number of switch ports.
Logic on the FPX module is implemented with two FPGA devices. The first device is used to interface between the switch and the line card, while the second is used to prototype new networking functions and protocols. The logic on the second FPGA can be reprogrammed dynamically via control cells sent over the network.
The flexibility of the FPX has made the card of interest for several networking applications. This year, fifty FPX hardware modules will be fabricated and distributed to researchers at eight universities around the country who are interested in experimenting with reprogrammable networks and per-flow queuing mechanisms. The FPX hardware will first be used to implement fast IP lookup algorithms and distributed input queueing.
- 1.J. W. Lockwood, "Illinois Pulsar-based Optical Interconnect (iPOINT)." http://ipoint.vlsi.- uiuc.edu, Sept. 1999.Google Scholar
- 2.J. W. Lockwood, H. Duan, J. J. Morikuni, S. M. Kang, S. Akkineni, and 1t. H. Campbell, "Scalable optoelectronic ATM networks: The iPOINT fully functional testbed," IEEE Journal of Lightwave Technology, pp. 1093-1103, June 1995.Google ScholarCross Ref
- 3.H. Duan, J. W. Lockwood, and S. M. Kang, "FPGA prototype queueing module for high performance ATM switching," in Proceedings of the Seventh Annual IEEE International ASIC Conference, (Rochester, NY), pp. 429-432, Sept. 1994.Google Scholar
- 4.M. J. Karol, M. G. Hluchyj, and S. P. Morgan, "Input vs. output queueing in space division packet switching," IEEE Tfunsactions on Communicationa, vol. Com-35, pp. 1347-1356, Dec. 1987.Google Scholar
- 5.H. Duan, J. W. Lockwood, S. M. Kang, and J. Will, "High-performance OC-12/OC-48 queue design prototype for input-buffered ATM switches," in IN- FOCOM'97, (Kobe, Japan), pp. 20--28, Apr. 1997. Google ScholarDigital Library
- 6.J. S. Turner, T. Chaney, A. Fingerhut, and M. Flucke, "Design of a Gigabit ATM switch," in INFOCOM'97, 1997. Google ScholarDigital Library
- 7.J. S. Turner, "Gigabit Technology Distribution Program." http:/www.arl.wustl.edu/- gigabitkits/kits.html, Aug. 1999.Google Scholar
- 8.W. N. Eatherton, "Hardware-Based Internet Protocol Prefix Lookups." thesis, Washington University in St. Louis, 1998.Google Scholar
- 9.M. Waldvogel, G. Varghese, J. Turner, and B. Plattner, "Scalable high speed IP routing table lookups," in Proceeeding8 of ACM SIGCOMM '97, pp. 25-36, September 1997. Google ScholarDigital Library
- 10.N. McKeown, V. Anantharam, and J. Walrand, "Achieving 100% throughput in an input-queued switch," in INFOCOM'96, Mar. 1996.Google Scholar
- 11.H. Duau, J. W. Lockwood, and S. M. Kang, "Matrix unit cell scheduler (MUCS) for input-buffered switches," IBEE Communication Letters, vol. 2, pp. 20-23, Jan. 1998.Google ScholarCross Ref
- 12.N. McKeown and A. Mekkittikul, "A practical scheduling algorithm to achieve 100% throughput in input-queued switches," in INFOCOM'98, (San Francisco), Apr. 1998.Google Scholar
- 13.N. McKeown, M. Izzard, A. Mekkittikul, B. Ellersick, and M. Horowitz, "The Tiny Tera: A packet switch core," in IBBE Micro, pp. 26-33, Jan. 1997. Google ScholarDigital Library
- 14.W. Westfeldt, "Intemet reconfignrable logic for creating web-enabled devices." Xilinx Xcell, Q1 1999.Google Scholar
- 15.S. Kelem, "Virtex configuration architecture advanced user's guide." Xilinx XAPP151, Sept. 1999.Google Scholar
Index Terms
- Field programmable port extender (FPX) for distributed routing and queuing
Recommendations
Reprogrammable network packet processing on the field programmable port extender (FPX)
FPGA '01: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arraysA prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extender (FPX), enables packet processing functions to be implemented as modular ...
A low-power field-programmable gate array routing fabric
This paper describes a new programmable routing fabric for field-programmable gate arrays (FPGAs). Our results show that an FPGA using this fabric can achieve 1.57 times lower dynamic power consumption and 1.35 times lower average net delays with only 9%...
Comments