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Formal hardware verification by integrating HOL and MDG
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 10th Great Lakes symposium on VLSI table of contents
Chicago, Illinois, United States
Pages: 23 - 28  
Year of Publication: 2000
ISBN:1-58113-251-4
Authors
V. K. Pisini  ECE Dept., Concordia University, Montreal, Canada
S. Tahar  ECE Dept., Concordia University, Montreal, Canada
P. Curzon  School of Computing Science, Middlesex University, London, UK
O. Ait-Mohamed  Nortel Networks, Ottawa, Canada
X. Song  IRO Dept., Université de Montreal, Montreal, Canada
Sponsors
Northwestern University : Northwestern University
SIGDA: ACM Special Interest Group on Design Automation
IEEE : Institute of Electrical and Electronics Engineers
Publisher
ACM  New York, NY, USA
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ABSTRACT

In order to overcome the limitations of automated tools and the cumbersome proof process of interactive theorem proving, we adopt a hybrid approach for formal hardware verification which uses the strengths of theorem proving (HOL) with powerful mathematical tools such as induction and abstraction, and the advantages of automated tools (MDG) which support equivalence checking and model checking. The MDG system is a decision diagram based verification tool, primarily designed for hardware verification. HOL is a theorem prover built on higher-order logic.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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K. Schneider and T. Kropf, "Verifying Hardware Correctness by Combining Theorem Proving and Model Checking," Tech. Rep. SFB358-C2-5/95, University of Karlsruhe, Karlsruhe, Germany, December 1995.
 
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M. Gordon, "Combining Deductive Theorem Proving with Symbolic State Enumeration." 21 Years of Hardware Verification, December 1998. Royal Society Workshop to mark 21 years of BCS FACS.
 
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Z. Zhou and i. Boulerice, MDG Tools (VI.0) User's Manual. Dept. of Computer Science, University of Montreal, Montreal, Canada, June 1996.
 
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P. Curzon, S. Tahar, and O. Ait-Mohamed, "Verification of the MDG Components Library in HOL," in Theorem Proving in Higher Order Logics: Emerging Trends (J. Grundy and M. Newey, eds.), (Australian National University, Canberra, Australia), pp. 31-45, September 1998.
 
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P. Curzon, "The Formal Verification of the Fairisle ATM Switching Element," Techical Report 329, Computer Laboratory, University of Cambridge, U.K., March 1994.


Collaborative Colleagues:
V. K. Pisini: colleagues
S. Tahar: colleagues
P. Curzon: colleagues
O. Ait-Mohamed: colleagues
X. Song: colleagues

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