S. Bobba
ABSTRACT
In this paper, we present high-performance bidirectional repeaters that recondition the signal waveform and reduce the signal degradation. We also present the application of these repeaters to the design of high-performance bidirectional busses. SPICE simulation results for long bidirectional interconnects show an almost linear increase in delay with repeaters compared to a quadratic increase in delay without repeaters. These repeaters are also applied to improve the performance of long AND domino gates. SPICE simulation results show a significant reduction in the delay of long AND domino gate with repeaters.
- 1.3. M. Rabaey, Digital integrated circuits. Upper Saddle River, N J: Prentice Hall, 1996. Google Scholar
Digital Library
- 2.C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer insertion for noise and delay optimization," in Proc. of DAC, pp. 362-367, 1998. Google ScholarDigital Library
- 3.I. Dobbelaere, M. Horowitz, and A. El Gamal, "Regenerative feedback repeaters for programmable interconnections," in Proc. of ISSCC, pp. 116-117, 1995.Google Scholar
- 4.T. Iima, M. Mizuno, T. Horiuchi, and M. Yamashina, "Capacitive coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI," IEEE Journal of solidstate circuits, vol. 31, no. 4, pp. 531-536, April 1996.Google ScholarCross Ref
- 5.M. Shoji, Theory of CMOS digital circuits and circuit failures. Princeton, N J: Princeton University Press, 1992.Google Scholar
Index Terms
- High-performance bidirectional repeaters
Recommendations
Designing high-performance thermally stable repeaters for nano-interconnects
To enhance their performance, various designs of carbon nanotube (CNT) interconnects were analyzed and compared with conventional copper interconnects. To ameliorate the propagation delay of very long interconnect lines, smart buffers are inserted as ...
Impact of high-k spacer on device performance of a junctionless transistor
The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in ...
Leakage-tolerant design techniques for high performance processors
ISPD '02: Proceedings of the 2002 international symposium on Physical designIn sub-100nm technology generation, transistor subthreshold leakage is 100-1000nA/μm for high performance microprocessor logic technology. As gate oxide thickness approaches sub-10Å regime, gate oxide leakage escalates to 10-100A/cm2. Junction leakages also ...
Comments