Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	"The AS/X User's Guide", copyright IBM Corporation, 1996.
	2	Jason Cong , Lei He , Cheng-Kok Koh , Patrick H. Madden, Performance optimization of VLSI interconnect layout, Integration, the VLSI Journal, v.21 n.1-2, p.1-94, Nov. 1996  [doi>10.1016/S0167-9260(96)00008-9 ]
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	7	A.B. Kahng And S. Muddu, "A General Methodology for Response and Delay Computations in VLSI Interconnects", University of California, Los Angeles, UCLA CS Dept. TR- 940015, 1994.
	8	A.B. Kahng and S. Muddu, "An Analytical Delay Model for RLC Interconnects", IEEE Trans. on Computer-Aided Design, 16(12) (1997), pp. 1507-1514.
	9	Rony Kay , Lawrence Pileggi, PRIMO: probability interpretation of moments for delay calculation, Proceedings of the 35th annual conference on Design automation, p.463-468, June 15-19, 1998, San Francisco, California, United States  [doi>10.1145/277044.277172]
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	12	Tao Lin, personal communication, December, 1999.
	13	Lawrence Pileggi, Timing metrics for physical design of deep submicron technologies, Proceedings of the 1998 international symposium on Physical design, p.28-33, April 06-08, 1998, Monterey, California, United States  [doi>10.1145/274535.274539]
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	15	J. Rubenstein, E Penfield, Jr., and M. A. Horowitz, "Signal Delay in RC Tree Networks", IEEE Trans. on Computer- Aided Design, CAD-2, (July 1983), pp. 202-211.
	16	Bogdan Tutuianu , Florentin Dartu , Lawrence Pileggi, An explicit RC-circuit delay approximation based on the first three moments of the impulse response, Proceedings of the 33rd annual conference on Design automation, p.611-616, June 03-07, 1996, Las Vegas, Nevada, United States  [doi>10.1145/240518.240634]

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