Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Franz Aurenhammer, Voronoi diagrams—a survey of a fundamental geometric data structure, ACM Computing Surveys (CSUR), v.23 n.3, p.345-405, Sept. 1991  [doi>10.1145/116873.116880]
	2	A.V. Ferris-Prabhu, "Defect size variations and their effect on the critical area of VLSI devices," IEEE J. of Solid State Circuits, SC-20,4, 878-880, Aug. 1985.
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	9	B. R. Mandava, "Critical Area for Yield Models", IBM Technical Report TR22.2436, 12 Jan 1982.
	10	Niagara: IBM Internal DRC and Shape Processing Tool.
	11	E. Papadopoulou and D.T. Lee, "Critical Area Computation via Voronoi Diagrams", IEEE Trans. on Computer-Aided Design, vol. 18, no.4, April 1999.
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	13	J. Pineda de Gyvez, C. Di, "IC Defect Sensitivity for Footprint-Type Spot Defects," IEEE Trans. on Computer-Aided Design, 11, noS, 638-658, May 1992.
	14	Franco P. Preparata , Michael I. Shamos, Computational geometry: an introduction, Springer-Verlag New York, Inc., New York, NY, 1985
	15	Jeffrey S. Rogenski, EXTRACTION OF BREAKS IN RECTILINEAR LAYOUTS BY PLANE SWEEPS (Master''s Thesis), University of California at Santa Cruz, Santa Cruz, CA, 1995
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	18	I. A. Wagner and I. Koren, "An Interactive VLSI CAD Tool for Yield Estimation," IEEE Trans. on Semiconductor ManufacturingVol. 8, No.2, 130-138, 1995.
	19	H. Walker and S.W. Director, " VLASIC: A yield simulator for integrated circuits," IEEE Trans. on Computer-Aided Design, CAD-5,4, 541-556, 1986.

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