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Analysis of composition complexity and how to obtain smaller canonical graphs
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th conference on Design automation table of contents
Los Angeles, California, United States
Pages: 681 - 686  
Year of Publication: 2000
ISBN:1-58113-187-9
Authors
J. Jain  Fujitsu Labs of America, Sunnyvale, CA
K. Mohanram  Department of Electrical and Computer Engineering, University of Texas, Austin, TX
D. Moundanos  Fujitsu Labs of America, Sunnyvale, CA
I. Wegener  Universitaet Dortmund, Lehrstuhl Informatik 2, 44221 Dortmund, Germany
Y. Lu  Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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ABSTRACT

We discuss an open problem in construction of Reduced Ordered Binary Decision Diagrams (ROBDDs) using composition, and prove that the worst case complexity of the construction is truly cubic. With this insight we show that the process of composition naturally leads to the construction of (even exponentially) compact partitioned-OBDDs (POBDDs) [12]. Our algorithm which incorporates dynamic partitioning, leads to the most general (and compact) form of POBDDs - graphs with multiple root variables. To show that our algorithm is robust and practical, we have analyzed some well known problems in Boolean function representation, verification and finite state machine analysis where our approach generates graphs which are even orders of magnitude smaller.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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B. Bollig and I. Wegener. "Partitioned BDDs vs. Other BDD Models" Proc. IWLS, 1997.
 
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O. Coudert, C. Berthet, and J. Madre. "Verification of Sequential Machines Using Boolean Functional Vectors". Formal VLSI Correctness Verification. Elsevier Sc., pages 179-196, 1990.
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Y.V. Hoskote. "Formal Techniques for Verification of Synchronous Sequential Circuits". Ph.D Dissertation, Dept. of Electrical and Computer Engineering, The University of Texas at Austin, 1995.
 
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J. Jain, J. Bitner, D. S. Fussell, and J. A. Abraham. "Functional partitioning for verification and related problems". Brown/MIT VLSI Conference, March 1992.
 
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C. Pixley. "A Theory and Implementation of Sequential Hardware Equivalence". IEEE Trans. on CAD, pages 1469-1494, 1992.
 
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R. Mukherjee, J. Jain, K. Takayama, M. Fujita, J. Abraham, and D. Fussell. "An Efficient Filter-based Approach for Combinational Verification". IEEE Transactions on Computer-Aided Design, Vol-18, Pages 1542-1557, November 1999.
 
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D. Sieling and I. Wegener "NC-Algorithms for Operations on Binary Decision Diagrams". Parallel Processing Letters, 3:3-12, 1993.


Collaborative Colleagues:
J. Jain: colleagues
K. Mohanram: colleagues
D. Moundanos: colleagues
I. Wegener: colleagues
Y. Lu: colleagues

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