A bus delay reduction technique considering crosstalk

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A bus delay reduction technique considering crosstalk

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 441 - 445

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Kei Hirose	Department of Computer Science and Communication Engineering, Kyushu University, Kasuga Koen 6-1, Kasuga, Fukuoka 816-8580, Japan
Hiroto Yasuura	Department of Computer Science and Communication Engineering, Kyushu University, Kasuga Koen 6-1, Kasuga, Fukuoka 816-8580, Japan

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 16, Citation Count: 15

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 15

	Chunjie Duan , Sunil P. Khatri, Exploiting Crosstalk to Speed up On-Chip Buses, Proceedings of the conference on Design, automation and test in Europe, p.20778, February 16-20, 2004
	Jae-sun Seo , Dennis Sylvester , David Blaauw , Himanshu Kaul , Ram Krishnamurthy, A robust edge encoding technique for energy-efficient multi-cycle interconnect, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Bret Victor , Kurt Keutzer, Bus encoding to prevent crosstalk delay, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Maged Ghoneima , Yehea Ismail, Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Roshan Weerasekera , Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen, Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
	Ketan N. Patel , Igor L. Markov, Error-correction and crosstalk avoidance in DSM busses, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
	D. Deschacht , G. Servel, On-chip interconnections: impact of adjacent lines on timing, Proceedings of the 2001 conference on Asia South Pacific design automation, p.539-544, January 2001, Yokohama, Japan
	Ketan N. Patel , Igor L. Markov, Error-correction and crosstalk avoidance in DSM busses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1076-1080, October 2004
	Jean-Marc Philippe , Sébastien Pillement , Olivier Sentieys, Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects, Proceedings of the 7th International Symposium on Quality Electronic Design, p.334-339, March 27-29, 2006
	M. Ghonemia , Y. Ismail, Formal derivation of optimal active shielding for low-power on-chip buses, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.800-807, November 07-11, 2004
	Tudor Murgan , Massoud Momeni , Alberto García Ortiz , Manfred Glesner, A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Atsushi Sakai , Takashi Yamada , Yoshifumi Matsushita , Hiroto Yasuura, Reduction of coupling effects by optimizing the 3-D configuration of the routing grid, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.951-954, October 2003
	Edwin Naroska , Shanq-Jang Ruan , Uwe Schwiegelshohn, Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.4, p.421-425, April 2006
	Razak Hossain , Fabrizio Viglione , Marco Cavalli, Designing fast on-chip interconnects for deep submicrometer technologies, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.276-280, April 2003
	M. Ghoneima , Y. Ismail , M. Khellah , J. Tschanz , V. De, Serial-link bus: a low-power on-chip bus architecture, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.541-546, November 06-10, 2005, San Jose, CA