ACM Home Page
Please provide us with feedback. Feedback
Cache conscious data layout organization for embedded multimedia applications
Full text PdfPdf (146 KB)
Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Munich, Germany
Pages: 686 - 693  
Year of Publication: 2001
ISBN:0-7695-0993-2
Authors
C. Kulkarni  IMEC, Kapeldreef 75, B-3001 Leuven, Belgium and Katholieke Universiteit Leuven
C. Ghez  IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
M. Miranda  IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
F. Catthoor  IMEC, Kapeldreef 75, B-3001 Leuven, Belgium and Katholieke Universiteit Leuven
H. de Man  IMEC, Kapeldreef 75, B-3001 Leuven, Belgium and Katholieke Universiteit Leuven
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 14,   Citation Count: 8
Additional Information:

references   cited by   index terms   collaborative colleagues   peer to peer  

Tools and Actions: Review this Article  
Save this Article to a Binder    Display Formats: BibTex  EndNote ACM Ref   

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
P.Baglietto, M.Maresca and M.Migliardi, "Image processing on highperformance RISC systems", Proc. of the IEEE, vol. 84, no. 7, pp.917- 929, july 1996.
 
2
 
3
P.Clauss, B.Meister, "Automatic memory layout transformation to optimize spatial locality in parametrized loop nests", 4th Annual Workshop on Interaction between Compilers and Comp. Arch. (INTERACT- 4), Toulouse, France, Jan 2000.
 
4
J.Covino, J.Connor, D.Evans, A.Roberts, M.Robillard, J.Sousa, L.Ternullo, "A 2ns zero wait state, 32KB semi-associative L1 cache", IEEE Intl Solid State Circuits Conference (ISSCC-96), pp. 154-155, 1996.
 
5
E.De Greef, "Storage size reduction for multimedia applications", Doctoral Dissertation, Dept. of EE, K.U.Leuven, January 1998.
 
6
 
7
C.Ghez, M.Miranda, A.Vandecappelle, F.Catthoor, D.Verkest, "Systematic high-level address code transformations for piece-wise linear indexing: illustration on a medical imaging algorithm", Proc. IEEE Wsh. on Signal Processing Systems (SIPS), Lafayette LA, IEEE Press, Oct. 2000.
8
 
9
N.Jouppi, et al. , "A 300-MHz 115-W 32-b bipolar ECL microprocessor", In IEEE Journal of solid-state circuits, pp. 1152-1165, Nov 1993.
 
10
 
11
 
12
C.Kulkarni, F.Catthoor, H.De Man, "Cache optimization for multimedia applications", Doctoral Dissertation, Dept. of EE, K.U.Leuven, February 2001.
 
13
 
14
D.Kulkarni, M.Stumm, "Linear loop transformations in optimizing compilers for parallel machines", The Australian computer journal, pp.41-50, may 1995.
15
 
16
N.Manjikian and T.Abdelrahman, "Array data layout for reduction of cache conflicts", Intl. Conference on Parallel and Distributed Computing Systems, 1995.
 
17
 
18
 
19
 
20
 
21
D.Burger, T.Austin, "The Simplescalar Toolset", Version 2.0, online document available at http://ww.cs.wisc.edu/ mscalar/simplescalar.html.

CITED BY  8
 
 
 
 
 

Collaborative Colleagues:
C. Kulkarni: colleagues
C. Ghez: colleagues
M. Miranda: colleagues
F. Catthoor: colleagues
H. de Man: colleagues

Peer to Peer - Readers of this Article have also read: