Shih-Hsu Huang
ABSTRACT
The demand for low power digital systems has motivated significant research. However, the power estimation at the logic level is a difficult task because interconnect plays a role in determining the total chip power dissipation. As a result, the power optimization at the logic level may be inaccurate due to the lack of physical place and route information. In this paper, we will present an effective low power design methodology based on interconnect prediction at the logic level. The proposed design methodology includes the method to create wire load models and the design procedures to select the appropriate wire load model during synthesis. The main distinction of the proposed approach is that it constructs physical hierarchy during the synthesis stage. By taking advantage of wire load models, the proposed design methodology is able to develop low power digital systems while speeding up the design process. Experimental data shows that this design methodology achieved very good results.
- 1.A. Tyagi. Hercules: A Power Analysis of MOS VLSI Circuits. in the Proc. of ICCAD, pages 530-533, 1987.Google Scholar
- 2.Avant! Inc. Apollo User Guide. 1998.Google Scholar
- 3.Avant! Inc. IC Layout Getting Started Guide. 1995.Google Scholar
- 4.Cadence Inc. SDF Toolkit Reference Manual. 1991.Google Scholar
- 5.C.H. Chien. CCL 0.35~m Standard Cell Library. in Technical Journal of Computer & Communication Research Laboratories, pages 32-40, Volume 72, 1998.Google Scholar
- 6.D. Dobberpuhl, et. al. A 200MHz, 64b, Dual Issue CMOS Microprocessor. Digest of Technical papers, ISSC'92, pages 106-107, 1992.Google Scholar
- 7.J.M. Tseng, S.H. Huang, et. al. The Creation and Application of Wire Load Model. in Technical Journal of Computer & Communication Research Laboratories, pages 21-27, Volume 62, 1997.Google Scholar
- 8.L. Benini, M. Favalli, and B. Ricco. Analysis of Hazard Contribution to Power Dissipation in CMOS ICs. in the Proc. of International Workshop on Low Power Design, pages 27-32, 1994.Google Scholar
- 9.M.C. Chi, C.M. Tseng, C.Y. Lee, and S.H. Huang. An Interconnect Driven ASIC Design Procedure. in the Proc. of 11th Annual International ASIC Conference, pages 233-237, 1998.Google Scholar
- 10.N.H.E. Weste and K. Eshraghian. Principles of CMOS VLSI Design: A System Perspective. Addison Wesley, 1993. Google ScholarDigital Library
- 11.S.M. King. Accurate Simulation of Power Dissipation in VLSI Circuits. in IEEE Journal of Solid State Circuits, 21(5):889-891, 1986.Google ScholarCross Ref
- 12.S. Rajgopal and G. Mehta. Experiences with Simulation-Based Schematic Level Current Estimation. in the Proc. of International Workshop on Low Power Design, pages 129-134, 1995.Google Scholar
- 13.Synopsys Inc. Power Management in High-Level Design. 1996.Google Scholar
- 14.Synopsys Inc. Deep Submicron Technology Design Methodology. 1995.Google Scholar
- 15.Synopsys Inc. PowerGate Manual. 1997.Google Scholar
- 16.Synopsys Inc. Synopsys Link-to-Layout Methodology Flow Application Note. 1996.Google Scholar
- 17.S.H. Huang, K.C. Jung, et. al. Links-to-Layout Design Environment. in Technical Journal of Computer & Communication Research Laboratories, Volume 52, 1996.Google Scholar
- 18.S.H. Huang. A Design Methodology for a 0.35~m IC Project. in Technical Journal of Computer & Communication Research Laboratories, pages 42-47, Volume 82, 1999.Google Scholar
Index Terms
- An effective low powr design methodology based on interconnect prediction
Recommendations
Fast floorplanning for effective prediction and construction
Floorplanning is a crucial phase in VLSI physical design. The subsequent placement and routing of the cells/modules are coupled very closely with the quality of the floorplan. A widely used technique for floorplanning is simulated annealing. It gives ...
Sequential delay budgeting with interconnect prediction
Delay budgeting is a process of determining upper bounds for net delays to guide timing-driven placement. The existing approaches deal de facto only with combinational circuits. However, incorporating retiming into delay budgeting introduces more ...
Revisiting inherent noise floors for interconnect prediction
SLIP '20: Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding WorkshopToday's synthesis, placement and routing (SP&R) tools routinely handle millions of instances. Accurate prediction of outcomes is needed to avoid long wasted runtimes from, e.g., unroutable floor-plans or placements. However, tool outputs have inherent ...
Comments