Integrating superscalar processor components to implement register caching

ABSTRACT

A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a large logical register file can be slow, particularly in the context of a wide-issue processor which requires an even larger physical register file, and many read and write ports. Previous work has suggested that a register cache can be used to address this problem. This paper proposes a new register caching mechanism in which a number of good features from previous approaches are combined with existing out-of-order processor hardware to implement a register cache for a large logical register file. It does so by separating the logical register file from the physical register file and using a modified form of register renaming to make the cache easy to implement. The physical register file in this configuration contains fewer entries than the logical register file and is designed so that the physical register file acts as a cache for the logical register file, which is the backing store. The tag information in this caching technique is kept in the register alias table and the physical register file. It is found that the caching mechanism improves IPC up to 20% over an un-cached large logical register file and has performance near to that of a logical register file that is both large and fast.

REFERENCES

• 1: Douglas C. Burger and Todd M. Austin. The SimpleScalar Tool Set, Version 2.0. University of Wisconsin, Madison Tech. Report. June, 1997.
• 2: José-Lorenzo Cruz , Antonio González , Mateo Valero , Nigel P. Topham, Multiple-banked register file architectures, Proceedings of the 27th annual international symposium on Computer architecture, p.316-325, June 2000, Vancouver, British Columbia, Canada
• 3: Antonio González , Mateo Valero , José González , Teresa Monreal, Virtual Registers, Proceedings of the Fourth International Conference on High-Performance Computing, p.364, December 18-21, 1997
• 4: A. González , J. González , M. Valero, Virtual-Physical Registers, Proceedings of the 4th International Symposium on High-Performance Computer Architecture, p.175, January 31-February 04, 1998
• 5: Linley Gwenapp. Digital 21264 Sets New Standard. Microprocessor Report, Vol. 10, No. 14. October 28, 1996, pp. 11-16.
• 6: Intel IA-64 Application Developer's Architecture Guide. May 1999. Order Number: 245188-001. Available at http://developer.intel.com/design/ia64/devinfo.htm.
• 7: Jack L. Lo , Sujay S. Parekh , Susan J. Eggers , Henry M. Levy , Dean M. Tullisen, Software-Directed Register Deallocation for Simultaneous Multithreaded Processors, IEEE Transactions on Parallel and Distributed Systems, v.10 n.9, p.922-933, September 1999 [doi>10.1109/71.798316 ]
• 8: Luis A. Lozano , Guang R. Gao, Exploiting short-lived variables in superscalar processors, Proceedings of the 28th annual international symposium on Microarchitecture, p.292-302, November 29-December 01, 1995, Ann Arbor, Michigan, United States
• 9: Milo M. Martin , Amir Roth , Charles N. Fischer, Exploiting dead value information, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.125-135, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 10: Teresa Monreal , Antonio González , Mateo Valero , José González , Victor Viñals, Delaying physical register allocation through virtual-physical registers, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.186-192, November 16-18, 1999, Haifa, Israel
• 11: Mayan Moudgill , Keshav Pingali , Stamatis Vassiliadis, Register renaming and dynamic speculation: an alternative approach, Proceedings of the 26th annual international symposium on Microarchitecture, p.202-213, December 01-03, 1993, Austin, Texas, United States
• 12: David A. Patterson , Carlo H. Sequin, RISC I: A Reduced Instruction Set VLSI Computer, Proceedings of the 8th annual symposium on Computer Architecture, p.443-457, May 12-14, 1981, Minneapolis, Minnesota, United States
• 13: Matthew Postiff, David Greene, Charles Lefurgy, Dave Helder, Trevor Mudge. The MIRV SimpleScalar/PISA Compiler. University of Michigan CSE Technical Report CSE-TR-421- 00, April 2000. Available at {22}.
• 14: Matthew Postiff, David Greene, and Trevor Mudge. Exploiting Large Register Files in General Purpose Code. University of Michigan Technical Report CSE-TR-434-00, October 2000. Available at {22}.
• 15: Matthew Allan Postiff , Trevor Mudge, Compiler and microarchitecture mechanisms for exploiting registers to improve memory performance, 2001
• 16: Dezsö Sima, The Design Space of Register Renaming Techniques, IEEE Micro, v.20 n.5, p.70-83, September 2000 [doi>10.1109/40.877952 ]
• 17: J. A. Swensen , Y. N. Patt, Hierarchical registers for scientific computers, Proceedings of the 2nd international conference on Supercomputing, p.346-354, June 1988, St. Malo, France [doi>10.1145/55364.55398]
• 18: CORPORATE UNIX Press, System V application binary interface (3rd ed.), Prentice-Hall, Inc., Upper Saddle River, NJ, 1993
• 19: Kenneth C. Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro, v.16 n.2, p.28-40, April 1996 [doi>10.1109/40.491460 ]
• 20: Robert Yung , Neil C. Wilhelm, Caching processor general registers, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.307-312, October 02-04, 1995
• 21: Robert Yung and Neil C. Wilhelm. Caching Processor General Registers. Sun Microsystems Laboratories Tech. Report. June, 1995.
• 22: http://www.eecs.umich.edu/mirv.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES

General Terms:
Algorithms, Design, Performance