ABSTRACT
For multiple coupled RLC nets, we formulate the min-area simultaneous shield insertion and net ordering SINO/NB-ν problem to satisfy the given noise bound. We develop an efficient and conservative model to compute the peak noise, and apply the noise model to a simulated-annealing (SA) based algorithm for the SINO/NB-ν problem. Extensive and accurate experiments show that the SA-based algorithm is efficient, and always achieves solutions satisfying the given noise bound. It uses up to 71\% and 30\% fewer shields when compared to a greedy based shield insertion algorithm and a separated shield insertion and net ordering algorithm, respectively. To the best of our knowledge, it is the first work that presents an in-depth study on the min-area SINO problem under an explicit noise constraint.
- 1.J. Cong and C.-K. Koh, "Interconnect layout optimization under higher-order RLC model," in ICCAD, 1997. Google ScholarDigital Library
- 2.T. Xue, E. S. Kuh, and Q. Yu, "A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies," in Proc. IEEE Multi-Chip Module Conf., pp. 117-121, 1996. Google ScholarDigital Library
- 3.Y. I. Ismail and E. G. Friedman, "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits," in DAC, 1999. Google ScholarDigital Library
- 4.L. He and K. M. Lepak, "Simultaneous shielding insertion and net ordering for capacitive and inductive coupling minimization," in ISPD, 2000. Google ScholarDigital Library
- 5.G. Zhong, H. Wang, C.-K. Koh, and K. Roy, "A twisted bundle layout structure for minimizing inductive coupling noise," in ICCAD, 2000. Google ScholarDigital Library
- 6.K. M. Lepak, I. Luwandi, and L. He, "Simultaneous shield insertion and net ordering under explicit noise constraint," Tech. Rep. ECE-00-006, University of Wisconsin, 2000.Google Scholar
- 7.L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An efficient inductance modeling for on-chip interconnects," in IEEE CICC, pp. 457-460, 1999.Google Scholar
- 8.J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali, and S. H.-C. Yen, "Analysis and justification of a simple, practical 2 1/2-d capacitance extraction methodology," in DAC, 1997. Google ScholarDigital Library
- 9.S. Lin, N. Chang, and O. S. Nakagawa, "Quick on-chip self- and mutual-inductance screen," in International Symposium on Quality of Electronic Design, 2000. Google ScholarDigital Library
Index Terms
- Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Recommendations
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
ICCAD '00: Proceedings of the 2000 international conference on Computer-aided designIn this paper, we first show that existing net ordering formulations to minimize noise are no longer valid with presence of inductive noise, and shield insertion is needed to minimize inductive noise. We then formulate two simultaneous shield insertion ...
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
In this article, we first show that existing net ordering formulations to minimize noise are no longer sufficient with the presence of inductive noise, and shield insertion is needed to minimize inductive noise. Using a Keff model as the figure of merit ...
Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction
SBCCI '03: Proceedings of the 16th symposium on Integrated circuits and systems designWith high clock frequencies, faster transistor rise/fall time, long signal wires, and the use of wider wires and Cu material interconnects, inductance of interconnect and the noise generated because of this inductance is becoming an important design ...
Comments