Predicting area-time tradeoffs for pipelined design

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Predicting area-time tradeoffs for pipelined design

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE conference on Design automation table of contents

Miami Beach, Florida, United States

Pages: 35 - 41

Year of Publication: 1987

ISBN:0-8186-0781-5

Authors

R. Jain	Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
A. Parker	Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
N. Park	Department of Electrical Engineering, University of California, Irvine, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 9

Additional Information:

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ABSTRACT

In this paper we give a model for predicting the shape of cost-speed tradeoff curves for pipelined designs. The model includes prediction of the number of operators, registers and multiplexers from a behavioral specification. It has been verified with the designs generated by an automated pipeline synthesis program, Sehwa. This model was developed as a part of the ADAM Advanced Design Automation System of the University of Southern California.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. "ir. Kung, "On Supercomputing with Systolic/Wavefront Array Processors", Proc. IEEE, Vol.72, No.7, July 1984.
	2	Fadi J. Kurdahi , Alice C. Parker, PLEST: a program for area estimation of VLSI integrated circuits, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.467-473, July 1986, Las Vegas, Nevada, United States
	3	Nohbyung Park , Alice Parker, Sehwa: a program for synthesis of pipelines, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.454-460, July 1986, Las Vegas, Nevada, United States
	4	John Granacki , David Knapp , Alice Parker, The ADAM advanced design automation system: overview, planner and natural language interface, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.727-730, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317970]

CITED BY 9

	Raul Camposano , Reinaldo A. Bergamaschi, Redesign using state splitting, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	Rajiv Jain , Alice Parker , Nohbyung Park, Module selection for pipelined synthesis, Proceedings of the 25th ACM/IEEE conference on Design automation, p.542-547, June 12-15, 1988, Atlantic City, New Jersey, United States
	Hong Shin Jun , Sun Young Hwang, Automatic synthesis of pipeline structures with variable data initiation intervals, Proceedings of the 31st annual conference on Design automation, p.537-541, June 06-10, 1994, San Diego, California, United States
	R. Jain , K. Kücükcakar , M. J. Mlinar , A. C. Parker, Experience with ADAM synthesis system, Proceedings of the 26th ACM/IEEE conference on Design automation, p.56-61, June 25-28, 1989, Las Vegas, Nevada, United States
	Smita Bakshi , Daniel D. Gajski, Design exploration for high-performance pipelines, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.312-316, November 06-10, 1994, San Jose, California, United States
	Viraphol Chaiyakul , Allen C.-H. Wu , Daniel D. Gajski, Timing models for high-level synthesis, Proceedings of the conference on European design automation, p.60-65, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	J. Ramanujam , Sandeep Deshpande , Jinpyo Hong , Mahmut Kandemir, A Heuristic for Clock Selection in High-Level Synthesis, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.414, January 07-11, 2002
	C. Papachristou , M. Nourani, False path exclusion in delay analysis of RTL-based datapath-controller designs, Proceedings of the conference on European design automation, p.336-341, September 1996, Geneva, Switzerland
	Mehrdad Nourani , Christos A. Papachristou, False path exclusion in delay analysis of RTL structures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.30-43, 2/1/2002