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Reference idempotency analysis: a framework for optimizing speculative execution
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Source Principles and Practice of Parallel Programming archive
Proceedings of the eighth ACM SIGPLAN symposium on Principles and practices of parallel programming table of contents
Snowbird, Utah, United States
Pages: 2 - 11  
Year of Publication: 2001
ISBN:1-58113-346-4
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Authors
Seon Wook Kim  Intel Corp., Champaign, IL and School of Electrical and Computer Engineering, Purdue University
Chong-liang Ooi  School of Electrical and Computer Engineering, Purdue University
Rudolf Eigenmann  School of Electrical and Computer Engineering, Purdue University
Babak Falsafi  Department of Electrical and Computer Engineering, Carnegie Mellon University
T. N. Vijaykumar  School of Electrical and Computer Engineering, Purdue University
Sponsor
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 4,   Downloads (12 Months): 19,   Citation Count: 4
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ABSTRACT

Recent proposals for multithreaded architectures allow threads with unknown dependences to execute speculatively in parallel. These architectures use hardware speculative storage to buffer uncertain data, track data dependences and roll back incorrect executions. Because all memory references access the speculative storage, current proposals implement this storage using small memory structures for fast access. The limited capacity of the speculative storage causes considerable performance loss due to speculative storage overflow whenever a thread's speculative state exceeds the storage capacity. Larger threads exacerbate the overflow problem but are preferable to smaller threads, as larger threads uncover more parallelism. In this paper, we discover a new program property called memory reference idempotency. Idempotent references need not be tracked in the speculative storage, and instead can directly access non-speculative storage (i.e., the conventional memory hierarchy). Thus, we reduce the demand for speculative storage space. We define a formal framework for reference idempotency and present a novel compiler-assisted speculative execution model. We prove the necessary and sufficient conditions for reference idempotency using our model. We present a compiler algorithm to label idempotent memory references for the hardware. Experimental results show that for our benchmarks, over 60% of the references in non-parallelizable program sections are idempotent.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Sun Microsystems. MAJC architecture tutorial. White Paper, September 1999.
 
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Collaborative Colleagues:
Seon Wook Kim: colleagues
Chong-liang Ooi: colleagues
Rudolf Eigenmann: colleagues
Babak Falsafi: colleagues
T. N. Vijaykumar: colleagues

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