Ansgar Stammermann
ABSTRACT
We present a software tool for power dissipation analysis and optimization on the algorithmic abstraction level from C/C++ and VHDL descriptions. An analysis is most efficient on such a high level since the influence of design decisions on the power demand increases with increasing abstraction [1]. The ORINOCO© tool enables to compare different but functionally equivalent algorithms and bindings to RT-level architectures with respect to power consumption. The results of the optimized binding can be used to guide synthesis. In the experimental evaluation we compare the predicted optimization trend with synthesized implementations and prove the accuracy of our methodology and tool.
- 1.A. Raghunathan, N.K. Niraj, S. Dey, "High-Level Power Analysis and Optimization", Kluwer Academic Publishers, 1998 Google Scholar
Digital Library
- 2.E. Macii, M. Pedram, F. Somenzi, "High Level Power Modeling, Estimation, and Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(11), pp. 1061 - 1079, November 1998 Google ScholarDigital Library
- 3.G. Jochens, L. Kruse, E. Schmidt, W. Nebel, "A New Parameterizable Power Macro-Model for Datapath Components", in Proc. for DATE, pp. 29-36, 1999 Google ScholarDigital Library
- 4.E. Schmidt, G. Jochens, L. Kruse, W. Nebel, "Automatic Nonlinear Memory Power Modelling", in Proc. for DATE, p. 808, 2001 Google ScholarDigital Library
- 5.L. Kruse, E. Schmidt, G. Jochens, A. Stammermann, A. Schulz, E. Macii, and W. Nebel, "Estimation of Lower and Upper Bounds on the Power Consumption from Scheduled Data Flow Graphs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems", pp. 3 - 14, February 2001 Google ScholarDigital Library
- 6.L. Kruse, E. Schmidt, G. Jochens, A. Stammermann, W. Nebel, "Low Power Binding Heuristics", PATMOS-99, pp. 41-50, 1999Google Scholar
- 7.A. Alvandpour, "Power Estimation and Low Power CMOS Circuit Techniques", Chapter 4, Link~ping Studies in Science and Technology, Dissertation Nr. 587, 1999Google Scholar
- 8.A. Alvandpour, P. Larsson-Edefors, C. Svenssons, "GLMC: Interconnect Length Estimation by Growth-Limited Multifold Clustering", Proceedings of IEEE International Symposium on Circuits and Systems, pp. V 465-8, Geneva, Switzerland, 2000Google ScholarCross Ref
- 9.A. Allara, M. Bombana, L. Kruse, E. Schmidt, A. Stammermann, "VHDL Behavioural Power Estimation for Telecom Devices", accepted at FDL, Lyon, September 2001Google Scholar
- 10.N. Dutt and C. Ramachandran, Benchmarks for the 1992 high level synthesis workshop, Tech. Rep. #92-107, Dep. Inform. Comput. Sci., Univ. California, Irvine, 1992Google Scholar
Index Terms
- System level optimization and design space exploration for low power
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