|
ABSTRACT
Retiming is a synchronous circuit transformation that can optimize the delay of a synchronous circuit by moving registers across combinational circuit elements. The combinational structure remains unchanged and the observable behavior of the circuit is identical to the original.In this paper, we address the problem of applying retiming techniques to circuits implemented in Field Programmable Gate Arrays (FPGAs). FPGAs contain prefabricated and configurable routing elements that allow us to easily implement a variety of circuits. However this interconnect contributes greatly to the overall delay in the implemented circuit. If a circuit is retimed prior to the placement and routing phases of the CAD flow, then it has no information about the delays introduced by the configurable interconnect. Our fundamental experiment is to determine whether there are any gains in tightly coupling retiming and placement so that the retiming algorithm has some estimate of the routing delays.Specifically, we introduce a post-placement retiming algorithm that understands how to take advantage of FPGA architectural features. This retiming algorithm may introduce extra registers into the circuit. These new registers need to be placed in some location in the FPGA. Retiming register placement is accomplished by a novel incremental clustering and placement algorithm. The incremental algorithm builds upon the placement of the non-retimed circuit to intelligently sift in the newly-introduced registers.In addition, we explore making the placement algorithms "retiming aware." These placement algorithms try to place logic blocks in such a way that the subsequent retiming produces better speed results. These techniques include the identification of retiming-critical cycles during placement.Our experiments show that the integration of retiming with placement results in 19% better clock periods in comparison to the application of retiming before the place and route steps.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Altera.ltera 2000 Databook .Available from: http://www.altera.com/html/literature/lds.html.
|
| |
2
|
|
| |
3
|
|
| |
4
|
B.Cherkassky and A.V.Goldberg.Negative cycle detection algorithms.Tech.Rep.tr-96-029,NEC Research Institute,Inc.,March 1996.
|
| |
5
|
J.Cong and Y.Ding.FlowMap:An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.IEEE Transactions on CAD ,pages 1 -12,Jan 1994.
|
| |
6
|
|
| |
7
|
C.Leiserson,F.Rose,and J.Saxe.Optimizing synchronous circuitry.Journal of VLSI and Computer Systems, pages 41 -67,1983.
|
| |
8
|
C.Leiserson and J.Saxe.Retiming synchronous circuitry.lgorithmica ,6(1):5 -35,1991.
|
| |
9
|
N.Maheshwari and S.S.Sapatnekar.Efficient retiming of large circuits.IEEE Transactions on VLSI Systems ,6(1):74 -83,1998.
|
 |
10
|
|
| |
11
|
|
| |
12
|
P.Pan,A.K.Karandikar,and C.L.Liu.Optimal Clock Period Clustering for Sequential Circuits with Retiming.Transactions on Computer-Aided Design, pages 489 -498,1998.
|
 |
13
|
|
| |
14
|
|
| |
15
|
Xilinx.Xilinx 2000 Databook .Available from: http://www.xilinx.com/partinfo/databook.htm.
|
CITED BY 18
|
|
|
|
|
|
|
|
|
|
Jason Cong , Yiping Fan , Xun Yang , Zhiru Zhang, Architecture and synthesis for multi-cycle communication, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
|
|
|
|
|
|
|
|
Nicholas Weaver , Yury Markovskiy , Yatish Patel , John Wawrzynek, Post-placement C-slow retiming for the xilinx virtex FPGA, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Peter Suaris , Lungtien Liu , Yuzheng Ding , Nanchi Chou, Incremental physical resynthesis for timing optimization, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
|
|
|
Peer to Peer - Readers of this Article have also read:
-
Data structures for quadtree approximation and compression
Communications of the ACM
28, 9
Hanan Samet
-
A hierarchical single-key-lock access control using the Chinese remainder theorem
Proceedings of the 1992 ACM/SIGAPP Symposium on Applied computing
Kim S. Lee
, Huizhu Lu
, D. D. Fisher
-
The GemStone object database management system
Communications of the ACM
34, 10
Paul Butterworth
, Allen Otis
, Jacob Stein
-
Putting innovation to work: adoption strategies for multimedia communication systems
Communications of the ACM
34, 12
Ellen Francik
, Susan Ehrlich Rudman
, Donna Cooper
, Stephen Levine
-
An intelligent component database for behavioral synthesis
Proceedings of the 27th ACM/IEEE conference on Design automation
Gwo-Dong Chen
, Daniel D. Gajski
|