Self-checking sequential circuits with self-healing ability

ABSTRACT

In this paper we deal with totally self-checking (TSC) synchronous sequential circuits (SSCs), that are able to recover after an occurrence of a fault. We call SSC owing this property as a self-healing SSC. A concept of a partially monotonic SSC is used in the paper. It is shown that the partially monotonic SSCs satisfy the self-healing property. A novel reduced m-out-of-n code is developed. It is proposed applying this code to the synthesis of a TSC checker for the state monotonic SSCs. The proposed method of synthesis is based on a LUT implementation of monotonic functions.For most circuits in a standard benchmark set, the proposed approach leads to a reduction of about 10-20% of the overhead as compared with the traditional methods.

References

1. 1.Akers, S. B., "A rectangular logic arrays," IEEE Trans. on Computers, Vol. C-21, August 1972, pp. 848-857.
2. 2.Lala, P., "Self-checking and Fault-Tolerant Digital Design", Morgan Kaufmann Publishers, San-Francisco / San-Diego / New-York/ Boston/ London/ Sydney/ Tokyo, 2000.
3. 3.Leveugle, R., and G. Saucier, "Optimized Synthesis of Concurrently Checked Controllers", IEEE Transactions on Computers, Vol. 39, No. 4, April 1990, pp. 419-425.
4. 4.Levin, I., A. Matrosova, S. Ostanin, "Survivable Selfchecking Sequential Circuits", Proc. of the Defect and Fault Tolerance in VLSI Systems Symposium, October 24-26, 2001, San Francisco, CA, USA, pp. 395-402.
5. 5.Levin, I., M. Karpovsky, "On-line Self-Checking of Microprogram Control Units", The 4th International On-line Testing Workshop, Capri, 1998, pp. 153-159.
6. 6.Levin, I., V. Sinelnikov, "Self-checking of FPGA based Control Units", Proceedings of 9th Great Lakes Symposium on VLSI, Ann Arbor, Michigan, 1999, IEEE press, pp. 292- 295.
7. 7.Matrosova A., S. Ostanin., "Self-checking FSM Design with Observing only FSM Outputs", Proc. The 6-th Int. On-Line Testing Workshop, July 2000, pp.153-154.
8. 8.Noubir, G., B. Y. Choueiry, "Algebraic Techniques for the Optimization of Control Flow Checking", Proc. of IEEE FTCS'96, 1996, pp. 128-137.
9. 9.Parekhji, R.A., G. Venkatesh, and S.D. Sherlekar, "Concurrent Error Detection Using Monitoring Machines", IEEE Design & Test of Computers, Vol. 12, No. 3, 1995, pp. 24-31.
10. 10.Paull, M.C., and S.H. Unger, "Minimizing the number of states in incompletely specified sequential switching functions", IRE Trans. Electron. Computers, V EC-8, No. 3, 1959, pp. 356-367.
11. 11.Smith, J.E., and G. Metze, "Strongly Fault Secure Logic Networks", IEEE Transaction on Computers, vol. C-27, June 1978, pp. 491-499.
12. 12.Smith, J., "On Separable Unordered Codes", IEEE Transaction on Computers, Vol. C-33, No. 8, August 1984, pp. 741-743.
13. 13.Tohma, Y., Y. Ohyama, R. Zakai, "Realization of fail-safe sequential machines by using a k-out-of-n code", IEEE Trans. Computers, Vol. c-20, N11, November 1971.

Index Terms

• Hardware

  • Hardware test

  • Integrated circuits

    • Logic circuits

      • Sequential circuits

  • Robustness