ABSTRACT
Designing semiconductor cluster tool systems is a complicated task due to the nature of automatic operations and various configurations of modules and task response priorities of robots. System designers have to synchronize the wafer processing time of each module with robot operation times in order to obtain maximum throughput from the system. A simulation model was developed to reflect the process flows of wafers to and from wafer carriers through various modules in the cluster tool system. The model was first utilized to ascertain the best system configuration of the proposed systems, then utilized to design a cluster tool system that will meet the specific customer requirements.
- Jefferson, T., M. Rangaswami, and G. Stoner. 1996. Simulation in the design of ground-based intrabay automation systems. In Proceedings of the 1996 Winter Simulation Conference, ed. J. M. Charnes, D. J. Morrice, D. T. Brunner, and J. J. Swain.1008-1013. Google ScholarDigital Library
- LeBaron, H. T. and M. Pool. 1994. The simulation of cluster tools: a new semiconductor manufacturing technology. In Proceedings of the 1994 Winter Simulation Conference, ed. J. D. Tew, S. Manivannan, D. A. Sadowski, and A. F. Seila.907-912 Google ScholarDigital Library
- Mason, S. J. and P. A. Jensen. 1996. A comparison study of the logic of four wafer fabrication simulators. In Proceedings of the 1996 Winter Simulation Conference, ed. J. M. Charnes, D. J. Morrice, D. T. Brunner, and J. J. Swain.1031-1038. Google ScholarDigital Library
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