ABSTRACT
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed test of high-speed microprocessors using low-cost testers. We explore the fault diagnosis capability of SBST, in which functional information can be used to guide and facilitate the generation of diagnostic tests. By using a large number of carefully constructed diagnostic test programs, the fault universe can be divided into fine-grained partitions, each corresponding to a unique pass/fail pattern. We evaluate the quality of diagnosis by constructing diagnostic-tree-based fault dictionaries. We demonstrate the feasibility of the proposed method by applying it to a processor example. Experimental results show its potential as an effective method for diagnosing larger processors.
- L. Chen and S. Dey, Software-based self-testing methodology for processor cores, IEEE Trans. Computer-Aided Design, vol.20, no.3, March 2001, pp. 369--380. Google ScholarDigital Library
- W.-C. Lai, A. Krstic, and K.-T. Cheng, On testing the path delay faults of a microprocessor using its instruction set, Proc. 18th VLSI Test Symp., Montreal, Canada, May 2000, pp. 15--20. Google ScholarDigital Library
- S. Almukhaizim, P. Petrov, and A. Orailoglu, Low-cost, software-based self-test methodologies for performance faults in processor control subsystems, Proc. IEEE 2001 Custom Integrated Circuits Conference, San Diego, CA, May 2001, pp. 263--6.Google ScholarCross Ref
- T. Grüning, U. Mahlstedt, and H. Koopmeiners, DIATEST: A fast diagnostic test pattern generator for combinational circuits, Proc. Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 1991, pp. 194--197.Google ScholarCross Ref
- S. Venkataraman and S.B. Drummonds, Poirot: applications of a logic fault diagnosis tool, IEEE Design & Test of Computers, vol.18, no.1, Jan.--Feb. 2001. pp. 19--30. Google ScholarDigital Library
- X. Yu, J. Wu, and E.M. Rudnick, Diagnostic test generation for sequential circuits, Proc. Int. Test Conf. 2000, Atlantic City, NJ, Oct. 2000, pp. 225--34. Google ScholarDigital Library
- I. Pomeranz and S.M. Reddy, A diagnostic test generation procedure based on test elimination by vector omission for synchronous sequential circuits, IEEE Trans. Computer-Aided Design, vol.19, no.5, May 2000, pp. 589--600. Google ScholarDigital Library
- J. Wu and E.M Rudnick, Bridge fault diagnosis using stuck-at fault simulation, IEEE Trans. Computer-Aided Design, vol.19, no.4, April 2000, pp. 489--495. Google ScholarDigital Library
- V. Boppana, I. Hartanto, and K. Fuchs, "Full fault dictionary storage based on labeled tree encoding, Proc. 14th VLSI Test Symp., Princeton, NJ, April 1996, pp. 174--9. Google ScholarDigital Library
- B. Chess and T. Larrabee, Creating small fault dictionaries, IEEE Trans. Computer-Aided Design, vol.18, no.3, March 1999, pp. 346--356. Google ScholarDigital Library
- Z. Navabi, VHDL: Analysis and modeling of digital systems, New York, McGraw-Hill, 1993. Google ScholarDigital Library
- http://esdat.ucsd.edu/~lichen/dac2002, additional information related to this paper.Google Scholar
Index Terms
- Software-based diagnosis for processors
Recommendations
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
VTS '00: Proceedings of the 18th IEEE VLSI Test SymposiumAt-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-test. However, due to their reliance on random patterns, current logic BIST ...
A scalable software-based self-test methodology for programmable processors
DAC '03: Proceedings of the 40th annual Design Automation ConferenceSoftware-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) that contain them. While early work on SBST has proposed several promising ...
Comments