Timing analysis challenges for high speed CPUs at 90nm and below

ABSTRACT

Advances of the VLSI technology into the sub-90nm processes, enabling complex CPU designs that work at GHz frequencies pose numerous design and verification challenges.In this invited presentation, we focus on challenges in timing analysis of CPUs working at GHz speeds and sub-90nm processes.We start by brief overview of Timing Analysis tool used for intel CPUs and the "shell" timing models used for large blocks and how they integrate into full-chip model. Hierarchical timing is emphasized as key enabler for handling full-chip timing.Next, short-term challenges are presented:

• Xtalk impact on timing
• Active interconnect
• Mixed abstraction, device to full-chip
• Use of domino as characterized cells.

An intermediate accuracy model for Xtalk is introduced, called SMCF, which adaptively adjust equivalent MCF of attackers based on slope relationship and an empiric formula.We go into some detail with an example of timing checks that need to be applied for domino cells, which are different from checks applied on static cells.Finally some mid-term challenges are described:

• Multiple Input Switching
• Process and environment variability
• Sleep transistors.

As variability is covered in more depth in other papers at this conference we mention it briefly but bring some examples of MIS and sleep transistor issues.