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ABSTRACT
In this paper we apply the concept of active shielding to inductive global interconnections. Active shields, which are shield wires that are switched at the same time as the signal wire, were initially developed to speed global signal propagation in RC dominated lines by ensuring in-phase switching of adjacent nets. This work further investigates this concept by examining RLC wiring. We find a distinct line width crossover point at which in-phase switching of neighbors no longer offers benefits and where the increased inductive behavior introduces substantial ringing. We propose the use of out-of-phase active shielding for such wide inductive lines. This technique is shown to significantly reduce ringing behavior (up to 4.5X) and offer better slopes (up to 40% reduction) and signal propagation delays, all of which are shown in the context of a clock net optimization.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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S. Morton, "On-chip Signaling", Special Topic Evening Session, International Solid State Circuits Conference (ISSCC), 2002.
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S. van Dijk and D. Hély, "Reduction of Interconnect Delay by Exploiting Cross-talk", Proceedings of European Solid State Circuits Conference, 2001.
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M. Kamon. M. Tsuk and J. White, "FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program", IEEE Transaction on MTT, Vol. 42, No. 9, pp. 1750--1758, September 1999.
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Yehia Massoud , Steve Majors , Tareq Bustami , Jacob White, Layout techniques for minimizing on-chip interconnect self inductance, Proceedings of the 35th annual conference on Design automation, p.566-571, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277194]
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P. Restle, et. al., "A Clock Distribution Network for Microprocessors", IEEE Journal of Solid State Circuits, Vol.36, pp 792--799, May 2001.
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