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Active shielding of RLC global interconnects
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Source Timing Issues In The Specification And Synthesis Of Digital Systems archive
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems table of contents
Monterey, California, USA
SESSION: Issues in crosstalk table of contents
Pages: 98 - 104  
Year of Publication: 2002
ISBN:1-58113-526-2
Authors
Himanshu Kaul  University of Michigan
Dennis Sylvester  University of Michigan
David Blaauw  University of Michigan
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 2,   Downloads (12 Months): 18,   Citation Count: 1
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ABSTRACT

In this paper we apply the concept of active shielding to inductive global interconnections. Active shields, which are shield wires that are switched at the same time as the signal wire, were initially developed to speed global signal propagation in RC dominated lines by ensuring in-phase switching of adjacent nets. This work further investigates this concept by examining RLC wiring. We find a distinct line width crossover point at which in-phase switching of neighbors no longer offers benefits and where the increased inductive behavior introduces substantial ringing. We propose the use of out-of-phase active shielding for such wide inductive lines. This technique is shown to significantly reduce ringing behavior (up to 4.5X) and offer better slopes (up to 40% reduction) and signal propagation delays, all of which are shown in the context of a clock net optimization.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
S. Morton, "On-chip Signaling", Special Topic Evening Session, International Solid State Circuits Conference (ISSCC), 2002.
2
 
3
S. van Dijk and D. Hély, "Reduction of Interconnect Delay by Exploiting Cross-talk", Proceedings of European Solid State Circuits Conference, 2001.
 
4
M. Kamon. M. Tsuk and J. White, "FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program", IEEE Transaction on MTT, Vol. 42, No. 9, pp. 1750--1758, September 1999.
5
 
6
P. Restle, et. al., "A Clock Distribution Network for Microprocessors", IEEE Journal of Solid State Circuits, Vol.36, pp 792--799, May 2001.


Collaborative Colleagues:
Himanshu Kaul: colleagues
Dennis Sylvester: colleagues
David Blaauw: colleagues

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