| A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology |
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International Symposium on Field Programmable Gate Arrays
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Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
table of contents
Monterey, California, USA
SESSION: Device-level design
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Pages: 145 - 153
Year of Publication: 2003
ISBN:1-58113-651-X
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Authors
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J. R. Guo
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Rensselaer Polytechnic Institute, Troy NY
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C. You
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Rensselaer Polytechnic Institute, Troy NY
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K. Zhou
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Rensselaer Polytechnic Institute, Troy NY
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B. S. Goda
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United State Military Academy, West Point, NY
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R. P. Kraft
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Rensselaer Polytechnic Institute, Troy NY
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J. F. McDonald
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Rensselaer Polytechnic Institute, Troy NY
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Downloads (6 Weeks): 1, Downloads (12 Months): 36, Citation Count: 2
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ABSTRACT
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but minimizing power consumption. The new SiGe process has traded off the circuit's performance for reduced power consumption. The power supply voltage has been reduced from 3.4 V to 2.0 V. The structure of the Basic Cell, including the Configurable Logic Block (CLB) and routing multiplexers (MUXs), has been modified so that the supply voltage reduction can be attained. Simulations have shown that the gate delay of the new Basic Cell is reduced from 130 ps in the prior design to 51 ps. The total power consumption for each Basic Cell has been reduced 94% from 71 mW to 4.2 mW, making a large scale FPGA feasible. This design is currently under fabrication for testing.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Bryan S. Goda, John F. McDonald, Stephen R. Carlough, Thomas W. Krawczyk Jr. and Russell P. Kraft, "IEE Proc.-Compu. Digi. Tech, vol.147, no. 3 pp. 189--194.
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Ken Martin, "Digital integrated circuit design", Oxford University Press Inc, pp 334.
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"IBM SiGe Designer's manual", (IBM Inc. Burlington Vermont. 2001)
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Greg Freeman et al, "40 Gb/s Circuits Built from a 120 GHz fT SiGe Technology", IEEE Journal of Solid State Circuits, vol. 9. September, 2002, pp. 1106--1114.
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Keiji Kishine, Yoshiji Kobayashi and Haruhiko Ichino, "A High Speed, Low-Power Bipolar Digital Circuit for Gb/s LSI's: Current Mirror Control Logic", IEEE Journal of Solid State Circuits, vol. 32 no. 2 February, 1997, pp. 215--221.
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Gerd Schuppener, Costantino Pala and Mehran Mokhtari, "Investigation on Low- Voltage Low- Power Silicon Bipolar Topology High Speed Digital Circuits", IEEE Journal of Solid State Circuits, vol. 35 no. 7 July 2000, pp. 1051--1054.
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CITED BY 2
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Jong-Ru Guo , C. You , P. F. Curran , M. Chu , K. Zhou , J. Diao , A. George , R P Kraft , J. F. McDonald, The 10GHz 4:1 MUX and 1:4 DEMUX implemented via the gigahertz SiGe FPGA, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
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Jong-Ru Guo , Chao You , Kuan Zhou , Michael Chu , Peter F. Curran , Jiedong Diao , Bryan Goda , Russell P. Kraft , John F. McDonald, A 10 GHz 4:1 MUX and 1:4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC, Integration, the VLSI Journal, v.38 n.3, p.525-540, January 2005
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