An FPGA architecture with enhanced datapath functionality

ABSTRACT

Although FPGAs are a cost-efficient alternative for both ASICs and general purpose processors, they still result in designs which are more than an order of magnitude more costly and slower than their equivalents implemented in dedicated logic. This efficiency gap makes FPGAs less suitable for high-volume cost-sensitive applications (e.g. embedded systems).We show that the intrinsic cost of traditional general-purpose FPGAs can be reduced if they are designed to target an application domain or a class of applications only. We propose a method of the application-domain characterization and apply it to characterize DSP. A novel FPGA logic block architecture derived based on such an analysis, and which exploits properties of target applications, is presented. Its key feature is the 'mixed-level granularity' being a trade-off between fine and coarse granularity required for the implementation of datapath and random logic functions, respectively. This leads to a factor of four improvement in the LUT memory size compared to commercial FPGAs, and, assuming a standard-cell implementation, a 1.6-2.8 lower datapath mapping cost. A modified mixed-grain architecture with the ALU-like functionality reduces the LUT memory size by a factor of 16 compared to commercial FPGAs, and mapped onto standard cells has a 1.9-3.3 times higher datapath mapping efficiency. For these reasons, the proposed FPGA architectures may be an interesting alternative to the traditional general-purpose FPGA devices, especially if characteristics of a target application domain are known a priority.

References

1. M. Agarwala and P. Balsara. An architecture for a DSP Field-Programmable Gate Array. IEEE Transactions on VLSI Systems, 3(1):136--141, March 1995.
2. Altera. FLEX 10KE Programmable Logic Device Family. Data sheet. Altera, 2000.
3. Altera. Stratix Programmable Logic Device Family. Data sheet. Altera, 2002.
4. Atmel. 5K-50K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRAM. Summary. Atmel, 1999.
5. N. F. Benschop. Symmetric logic synthesis with phase assignment. In Proc. of the 22nd Symposium on Information and Communication Theory, pp. 115--122. WIC, March 2001.
6. D. Cherepacha and D. Lewis. DP-FPGA: An FPGA architecture optimized for datapaths. VLSI Design, 4(4):329--343, 1996.
7. K. Compton and S. Hauck. Totem: Custom reconfigurable array generation. In Proc. of IEEE Symposium on FPGAs for Custom Computing Machines. IEEE, April 2001.
8. A. DeHon. Reconfigurable Architectures for General-Purpose Computing, AI Technical Report 1586, MIT Artificial Intelligence Laboratory. MIT, 545 Technology Sq., Cambridge, MA 02139, 1996.
9. V. George. Low Energy Field-Programmable Gate Array, Ph.D. Thesis. University of California, Berkeley, 2000.
10. J. He and J. Rose. Advantages of heterogeneous logic block architectures for FPGAs. In Proc. of IEEE Custom Integrated Circuits Conference. IEEE, May 1993.
11. D. Hill and N.-S. Woo. The benefits of flexibility in look-up table-based FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(2):349--353, February 1993.
12. A. Kaviani, D. Vranesic, and S. Brown. Computational Field Programmable Architecture. In Proc. of IEEE Custom Integrated Circuits Conference, pp. 261--264. IEEE, May 1999.
13. K. Leijten-Nowak, A. Katoch. Architecture and implementation of an embedded reconfigurable logic core in CMOS 0.13 μm. In Proc. of 15th IEEE ASIC/SOC Conference. IEEE, September 2002.
14. K. Leijten-Nowak and J. L. van Meerbergen. Applying the adder inverting property in the design of cost-efficient reconfigurable logic. In Proc. of 44th IEEE Midwest Symposium on Circuits and Systems. IEEE, August 2001.
15. K. Leijten-Nowak and J. L. van Meerbergen. Embedded reconfigurable logic core for DSP applications. In Proc. of Field-Programmable Logic and Applications Conference, pp. 89--101, September 2002.
16. A. Marshall, T. Stansfield, I. Kostarnov, J. Vuillemin, B. Hutchings. A Reconfigurable Arithmetic Array for multimedia applications. In Proc. of ACM Symposium on FPGAs, February 1999.
17. G. D. Michelli. Synthesis and Optmization of Digital Circuits. McGraw-Hill, Inc., 1994.
18. N. Miller and S. Quigley. A novel Field Programmable Gate Array architecture for high speed processing. In Proc. of Field-Programmable Logic and Applications Conference, pp. 386--390, September 1997.
19. J. R. K. C. G. P.-M. Paul~Chow, Soon Ong~Seo and I. Raharadja. The design of an SRAM-based Field-Programmable Gate Array. Part II: Circuit design and layout. IEEE Transactions on VLSI Systems, 7(3):101--110, September 1999.
20. J. Rabaey. Digital Integrated Circuits. A Design Perspective. Prentice Hall, 1996.
21. J. Rose, R. Francis, P. Chow, and D. Lewis. The effect of logic block complexity on area of programmable gate arrays. In Proc. of IEEE Custom Integrated Circuits Conference, pp. 5.3.1--5.3.5, May 1989.
22. J. R. Z. V. S.D. Brown, R.J. Francis. Field-Programmable Gate Arrays. Kluwer Academic Publishers, 1992.
23. T. Stansfield. Wordlength as an architectural parameter for reconfigurable computing devices. In Proc. of Field-Programmable Logic and Applications Conference, pp. 667--676, September 2002.
24. A. Telikapalli. Virtex-II Pro FPGAs: The platform for programmable systems has arrived. Xcell journal, 1(42):10--13, Spring 2002.
25. Xilinx. XC4000E and XC4000X Series Field Programmable Gate Arrays. Data sheet. Xilinx, 1999.
26. Xilinx. Virtex 2.5V Field Programmable Gate Arrays. Data sheet. Xilinx, 2000.
27. Xilinx. Virtex-II Pro Platform FPGAs. Data sheet. Xilinx, 2002.
28. R. Zimmermann. Lecture Notes on Computer Arithmetic: Principles, Architectures, and VLSI Design. Swiss Federal Institute of Technology. Integrated Systems Laboratory, Zurich, Switzerland, 1999.

Index Terms

• Hardware

  • Communication hardware, interfaces and storage

    • Signal processing systems

  • Integrated circuits

    • Logic circuits

  • Robustness

    • Design for manufacturability

      • Yield and cost modeling

      • Yield and cost optimization