ABSTRACT
This paper describes micro-optimization, a technique for reducing the operation count and time required to perform floating-point calculations. Micro-optimization involves breaking floating-point operations into their constituent micro-operations and optimizing the resulting code. Exposing micro-operations to the compiler creates many opportunities for optimization. Redundant normalization operations can be eliminated or combined. Also, scheduling micro-operations separately allows dependent operations to be partially overlapped. A prototype expression compiler has been written to evaluate a number of micro-optimizations. On a set of benchmark expressions operation count is reduced by 33% and execution time is reduced by 40%.
- 1.AMD, AMD 29000 User's Manual, 1987.Google Scholar
- 2.ANSI/iEEE Standard 754-1985, IEEE Standard for Binary Floating-Point Arithmetic.Google Scholar
- 3.Colwell, tL.P., et.al., "A VLiW Architecture for a Trace Scheduling Compiler," IEEE Trans. Computers, C- 37(8), August 1988, pp. 967-979. Google ScholarDigital Library
- 4.Coonen, jerome T., "An Implementation Guide to a Proposed Standard for Floating-Point Arithmetic," IEEE Computer, January 1980, pp. 68-79.Google ScholarDigital Library
- 5.Ilwang, K., Computer Arithmetic: Principles, Architecture, and Design, Wiley, 1979. Google ScholarDigital Library
- 6.Magenheimer, et.al., "Integer Multiplication and Division on the HP Precision Architecture," IEEE Trans. Computers, C-37(8), August 1988, pp. 980-990. Google ScholarDigital Library
- 7.Motorola, MC88100 $2-bit Third-Generation RI$C Microprocessor: Technical Summary, Document BR588/D, 1988.Google Scholar
- 8.Moussouris, J. et.al, "A CMOS RISC Processor with Integrated System Function," COMPCON, 1986, pp. 126-131.Google Scholar
- 9.Patterson, David A., "Reduced instruction Set Computers,'' CACM, 28(1), january 1985, pp. 8-21. Google ScholarDigital Library
- 10.Strecker, W.D., "VAX-11/780, A Virtual Address Extension to the PDP-11 Family", Proc. NCC, 1978, pp. 967-980.Google Scholar
- 11.Thornton, James E., "Parallel Operation in the Control Data 6600," Proc. AFIPS FJCC, vol 26, 1964, pp. 33- 40.Google Scholar
Index Terms
- Micro-optimization of floating-point operations
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