Reduced dynamic swing domino logic

ABSTRACT

A new reduced-swing domino logic technique is presented which provides significantly lower power dissipation as compared to traditional domino circuit structures. Additionally, the noise margins of the new circuit offer an improvement over standard domino design. The key idea of the new design style is to limit both the upper and lower bounds of the voltage swing at the internal dynamic node. The voltage swing at the inputs and the outputs of the domino circuit remains full-swing. A number of circuits are presented all of which have been designed and simulated in 0.18 micron technology. Analysis of simulation results show the potential for a 25-40% decrease in power consumption with an increased tolerance to noise. These improvements come at the expense of increased propagation delay and circuit area; the magnitude of which varies with the proposed circuit structures.

REFERENCES

• 1: Seong-Ook Jung , Ki-Wook Kim , Sung-Mo Kang, Low-swing clock domino logic incorporating dual supply and dual threshold voltages, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514036]
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design, Measurement, Performance