Exploiting multiple functionality for nano-scale reconfigurable systems

ABSTRACT

It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a result, these systems may come to be characterised by vast arrays of largely identical devices that are differentiated via post-fabrication configuration - but only if low-overhead configuration can be achieved. Two simulation studies are presented that describe some ideas for achieving low-overhead reconfigurability in systems built from nano-scale components. The first is based on variable-threshold devices built from thin-body double gate transistors while a second, more speculative idea is based on recently identified resonant tunneling behaviour in carbon nanotubes. Various logic functions can be configured via the application of a simple bias voltage. Further, two approaches to the issue of generating the required bias voltages based on RTD devices and chalcogenide films are briefly explored.

References

1. Akeyoshi, T., H. Matsuzaki, T. Itoh, T. Waho, J. Osaka, M. Yamamoto, Applications of Resonant-tunneling Diodes to High-speed Digital ICs. in Eleventh International Conference on Indium Phosphide and Related Materials, IPRM 1999, (1999), 405--410.
2. Bachtold, A., P. Hadley, T. Nakanishi, C. Dekker, Logic Circuits with Carbon Nanotube Transistors. Science, 294, 2001, 1317--1320.
3. Beckett, P., A Fine-Grained Reconfigurable Logic Array Based on Double Gate Transistors. in IEEE International Conference on Field-Programmable Technology, FPT2002, (Hong Kong, 2002).
4. Chang, L. Scaling Limits and Design Considerations for Double-Gate MOSFETs, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, 2001.
5. Chen, K.J., Waho, T., Maezawa, K., Yamamoto, M., An Exclusive-OR Logic Circuit Based on Controlled Quenching of Series-Connected Negative Differential Resistance Devices. IEEE Electron Device Letters, 17 (6), 1996, 309--311.
6. Collier, N.J., Cleaver, J. R. A., Novel Dual-Gate HEMT Utilising Multiple Split Gates. Microelectronic Engineering, 41-42, 1998, 457--460.
7. Collins, P.G., Bando, H. & Zettl, A, Nanoscale Electronic Devices on Carbon Nanotubes. in Fifth Foresight Conference on Molecular Nanotechnology, (1997), Foresight Institute.
8. Collins, P.G., Bradley, K., Ishigami, M., Zettl, A., Extreme Oxygen Sensitivity of Electronic Properties of Carbon Nanotubes. Science, 287, 2000, 1801--1804.
9. Compano, R. (ed.), Technology Roadmap for Nano-electronics. European Commission IST Programme - Future and Emerging Technologies, 2000.
10. DeHon, A., Array-Based Architecture for Molecular Electronics. in First Workshop on Non-Silicon Computation (NSC-1), (Cambridge, Mass., 2002).
11. Dequesnes, M., Rotkin, S. V., Aluru, N. R., Calculation of Pull-In Voltages for Carbon-Nanotube-Based Nano-electromechanical Switches. Nanotechnology, 13 (February 2002), 2002, 120--131.
12. Ding, J.W., X. H. Yan, J. X. Cao, Analytical Relation of Band Gaps to Both Chirality and Diameter of Single-Wall Carbon Nanotubes. Physical Review B (Condensed Matter and Materials Physics), 66 (073401), 2002.
13. Endoh, T., Sakuraba, H., Shinmei, K., Masuoka, F., New Three Dimensional (3D) Memory Array Architecture for Future Ultra High Density DRAM. in 22nd International Conference on Microelectronics, (2000), 447--450 vol.442.
14. Fossum, J.G., Chong, Y., Simulation-Based Assessment of 50 nm Double-Gate SOI CMOS Performance. in IEEE International SOI Conference, (Stuart, FL, USA, 1998), 107--108.
15. Gerousis, C., Goodnick, S.M., Xiaohui Wang, Porod, W., Csurgay, A.I., Toth, G., Lent, C.S., Modeling Nanoelectronic CNN Cells: CMOS, SETs and QCAs. in 2000 IEEE International Symposium on Circuits and Systems, ISCAS 2000, (Geneva., 2000), 274.
16. Goldstein, S.C., Electronic Nanotechnology and Reconfigurable Computing. in IEEE Computer Society Workshop on VLSI, (Orlando, Florida, 2001), IEEE, 10--15.
17. Goldstein, S.C., M. Budiu, NanoFabrics: Spatial Computing Using Molecular Electronics. in 28th International Symposium on Computer Architecture, (Goteborg, Sweden, 2001), IEEE, 178--189.
18. Heinze, S., J. Tersoff, R. Martel, V. Derycke, J. Appenzeller, Ph. Avouris, Carbon Nanotubes as Schottky Barrier Transistors. Physical Review Letters, 89 (106801), 2002, doi:10.1103/PhysRevLett.1189.106801.
19. Hobart, K.D., P. E. Thompson, S. L. Rommel, T. E. Dillon, P. R. Berger, D. S. Simons, P. H. Chi, "P-on-N" Si Interband Tunnel Diode Grown by Molecular Beam Epitaxy. Journal of Vacuum Science and Technology B, 19, 2001, 290--293.
20. Ieong, M., Jones, E.C., Kanarsky, T., Ren, Z., Dokumaci, O., Roy, R.A., Shi, L., Furukawa, T., Taur, Y., Miller, R.J., Wong, H.-S.P., Experimental Evaluation of Carrier Transport and Device Design for Planar Symmetric/ Asymmetric Double-Gate/Ground-Plane CMOSFETs. in Electron Devices Meeting, 2001. IEDM Technical Digest. International, (Washington, DC, 2001), 6.1--6.4.
21. Ishibashi, K., Ida, T., Suzuki, M., Tsukagoshi, K., Aoyagi, Y., Quantum Dots in Carbon Nanotubes. Japanese Journal of Applied Physics, 39 (12B), 2000, 7053--7057.
22. Jin, N., Paul R. Berger, Sean L. Rommel, Phillip E. Thompson, Karl D. Hobart, A PNP Si Resonant Interband Tunnel Diode with Symmetrical NDR. Electronics Letters, 37, 2001, 1412--1414.
23. Kado, Y., The Potential of Ultrathin-Film SOI Devices for Low-Power and High-Speed Applications. IEICE Transactions on Electronics, E80-C (3), 1997, 443--454.
24. Khakifirooz, A., Antoniadis, D.A., Effect of Back-Gate Biasing on the Performance and Leakage Control in Deeply Scaled SOI MOSFETs. in IEEE International SOI Conference, (2002), 58--59.
25. Lent, C.S., Tougaw, P. D., Porod, W., Bernstein, G. H., Quantum Cellular Automata. Nanotechnology, 4 (1), 1993, 49--57.
26. Léonard, F., J. Tersoff, Multiple Functionality in Nanotube Transistors. Physical Review Letters, 88, 2002, 258302.
27. Lowrey, T. Ovonic Unified Memory, Ovonyx Pty. Ltd., Troy, Michigan, U.S.A., 2001.
28. Maimon, J., E. Spall, R. Quinn, S. Schnur, Chalcogenide-Based Non-Volatile Memory Technology. in IEEE Aero-space Conference, (Big Sky, MT, USA, 2001), 2289--2294.
29. Maimon, J., K. Hunt, J. Rodgers, L. Burcin, K. Knowles. Integration and Circuit Demonstration of Chalcogenide Memory Elements with a Radiation Hardened CMOS Technology, Ovonix Corp., 2001.
30. Martel, R., T. Schmidt, H. R. Shea, T. Hertel, P. H. Avouris, Single and Multi-wall Nanotube Field-Effect Transistors. Applied Physics Letters, 73 (17), 1998, 2447--2449.
31. McEuen, P.L., Fuhrer, M.S., Hongkun Park, Single-Walled Carbon Nanotube Electronics. IEEE Transactions on Nanotechnology, 1 (1), 2002, 78--85.
32. McEuen, P.L., Park, J., Bachtold, A., Woodside, M., Fuhrer, M.S., Bockrath, M., Shi, L., Majumda, A., Kim, P., Nanotube Nanoelectronics. in Device Research Conference, (2001), 107--110.
33. McFarland, G.W., CMOS Technology Scaling and its Impact on Cache Delay, PhD thesis, Electrical Engineering,Stanford University, 1997.
34. Nakayama, K., K. Kojima, F. Hayakawa, Y. Imai, A. Kitagawa, M. Suzuki, Submicron Nonvolatile Memory Cell Based on Reversible Phase Transition in Chalcogenide Glasses. Japanese Journal Applied Physics, 39 (Part 1, No. 11), 2000, 6157--6161.
35. Niemier, M.T., Arun F. Rodrigues, Peter M. Kogge, A Potentially Implementable FPGA for Quantum Dot Cellular Automata. in First Workshop on Non-Silicon Computation, NSC-1, (Cambridge, Mass., 2002).
36. Niemier, M.T., P. M. Kogge, Logic in Wire: Using Quantum Dots to Implement a Microprocessor. in 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS '99, (Pafos, Cyprus, 1999), 1211--1215.
37. Parihar, V., R. Singh, K. F. Poole, Silicon Nanoelectronics: 100nm Barriers and Potential Solutions. in IEEE/SEMI Advanced Semiconductor Manufacturing Conference, (1998), IEEE, 427--121.
38. Ren, Z., R. Venugopal, S. Datta, M. Lundstrom, D. Jovanovic, J. Fossum. Idealized SOI-Si Double Gate NMOSFET Device, Rev. 12-8-00, Purdue University, Motorola, University of Florida, 2000.
39. Ren, Z., Ramesh Venugopal, Supriyo Datta, Mark Lundstrom, Examination of Design and Manufacturing Issues in a 10 nm Double Gate MOSFET using Nonequilibrium Green's Function Simulation. 2001.
40. Richter, R., H. Boeve, L. Bär, J. Bangert, G. Rupp, G. Reiss, J. Wecker, Field Programmable Spin-Logic Realized with Tunnelling-Magnetoresistance Devices. Solid-State Electronics, 46 (5), 2002, 639--643.
41. Rueckes, T., K. Kim, E. Joselevich, G. Y. Tseng, C-L. Cheung, C. M. Lieber, Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing. Science, 289, 2000, 94--97.
42. Schulz, T., W. Rösner, E. Landgraf, L. Risch, U. Langmann, Planar and Vertical Double Gate Concepts. Solid-State Electronics, 46 (7), 2002, 985--989.
43. Seabaugh, A.C., Y.-C. Kao, H.-T. Yuan, Nine-state Resonant Tunneling Diode Memory. IEEE Electron Device Letters, 13 (9), 1992, 479--481.
44. Stock, J., Malindretos, J., Indlekofer, K.M., Pottgens, M., Forster, A., Luth, H., A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits. IEEE Transactions on Electron Devices, 48 (6), 2001, 1028--1032.
45. Suzuki, M.I., K., Ida, T., Aoyagi, Y., Quantum Dot Formation in Single-Wall Carbon Nanotubes. Japanese Journal Applied Physics, 40, Part 1 (3B), 2001, 1915--1917.
46. Tucker, J.R., Schottky Barrier MOSFETS for Silicon Nanoelectronics. in Advanced Workshop on Frontiers in Electronics, WOFE '97, (1997), 97--100.
47. van der Wagt, J.P.A., Tunnelling-Based SRAM. Nanotechnology, 10 (2), 1999, 174--186.
48. Waho, T., Chen, K.J., Yamamoto, M., Resonant-tunneling Diode and HEMT Logic Circuits with Multiple Thresholds and Multilevel Output. IEEE Journal of Solid-State Circuits, 33 (2), 1998, 268--274.
49. Wei, S.-J., Lin, H.C., Multivalued SRAM Cell Using Resonant Tunneling Diodes. IEEE Journal of Solid-State Circuits, 27 (2), 1992, 212--216.
50. Wind, S.J., Appenzeller, J., Martel, R., Derycke, V., Avouris, Ph., Vertical Scaling of Carbon Nanotube Field-Effect Transistors using Top Gate Electrodes. Applied Physics Letters, 80 (20), 2002, 3817--3819.

Index Terms

• Hardware

  • Emerging technologies

  • Very large scale integration design