ACM Home Page
Please provide us with feedback. Feedback
A hybrid adiabatic content addressable memory for ultra low-power applications
Full text pdf formatPdf (95 KB)
Source Great Lakes Symposium on VLSI archive
Proceedings of the 13th ACM Great Lakes symposium on VLSI table of contents
Washington, D. C., USA
POSTER SESSION: Poster session 1 table of contents
Pages: 72 - 75  
Year of Publication: 2003
ISBN:1-58113-677-3
Authors
Aiyappan Natarajan  University of Massachusetts Amherst, MA
David Jasinski  University of Massachusetts Amherst, MA
Wayne Burleson  University of Massachusetts Amherst, MA
Russell Tessier  University of Massachusetts Amherst, MA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 0,   Downloads (12 Months): 25,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues   peer to peer  

Tools and Actions: Review this Article  
Save this Article to a Binder    Display Formats: BibTex  EndNote ACM Ref   
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/764808.764828
What is a DOI?

ABSTRACT

This paper presents a hybrid adiabatic content addressable memory (CAM). The CAM uses an adiabatic switching technique to reduce the energy consumption in the match line while keeping the performance for the read/write operation. The adiabatic CAM is suitable for ultra low-power, low performance applications such as smart cards and portable devices. This CAM uses a clocked power supply for the match line while the rest of the circuit is the same as the basic CAM. A novel smart card application which uses the adiabatic CAM is illustrated. The circuit simulations for a 16x16 and 32x32 CAM were done in Hspice using 0.18 μm Berkeley models and the energy dissipation was compared with a basic CAM. The results show three orders of magnitude in energy savings for the 16x16 CAM and one order of magnitude savings for the 32x32 CAM when operated at 2Mhz. The maximum frequency of operation for which there was considerable energy savings was found to be 200 Mhz with a 20% and 45% energy savings for 16x16 and 32x32 CAM respectively.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
A. J. McAuley and P. Francis. Fast routing table lookup using CAMs. IEEE INFOCOM 1993 pages 1382--1391, March 1993.
 
2
Berkeley Predictive Model, Univ. of California Berkeley. http://www-device.eecs.berkeley.edu/ptm/.
 
3
C. Ziesler, J. Kim, M. Papaefthymiou. Energy recovery asic design. ISVLSI pages 133--138, 2003.
4
 
5
G. Thirugnanam, N. Vijaykrishnan and M. J. Irwin. A novel low power CAM design. Proc. of the Fourteenth Annual IEEE Int'l ASIC/SOC Conf. pages 198--202, Sept 2001.
 
6
7
 
8
9
 
10
D. Somasekhar, Y. Ye, and K. Roy. An energy recovery static RAM memory core. In ISLPED pages 62--63, 1995.
 
11
V. Oklobdzija and D. Maksimovic. Pass-transistor adiabatic logic using single power-clock supply. IEEE TCAS - II 44(10):842--846, Oct 1997.
 
12
 
13
C. Zukowski and S. Wang. Use of selective precharge for low-power CAMs. IEEE ISCAS pages 745--770, Nov. 1993.

Collaborative Colleagues:
Aiyappan Natarajan: colleagues
David Jasinski: colleagues
Wayne Burleson: colleagues
Russell Tessier: colleagues

Peer to Peer - Readers of this Article have also read: