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54x54-bit radix-4 multiplier based on modified booth algorithm

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Published:28 April 2003Publication History

ABSTRACT

In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 28-2, 27-2, ..., and 10-2 compressors, and XOR based adder are proposed. While the whole design is coded in Verilog-HDL language and implemented through commercially available EDA tool chain, the implementation gives comparable results to full custom designs [1][2]. Realistic simulations using extracted timing parameters from the layout show that the propagation time of a critical path is 3.25ns at 2.5V on a 0.18um process technology, which is almost 21% faster than the conventional multiplier [2].

References

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  9. Hagihara. Y, et al., "A 2.7ns 0.25um CMOS 54x54 b multiplier", Solid-State Circuits Conference, 1998, Digest of Technical papers, 45th ISSCC 1998 IEEE International, pp. 296--297, 5-7 Feb 1998.Google ScholarGoogle Scholar
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          cover image ACM Conferences
          GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI
          April 2003
          320 pages
          ISBN:1581136773
          DOI:10.1145/764808

          Copyright © 2003 ACM

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          Publication History

          • Published: 28 April 2003

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