A novel 32-bit scalable multiplier architecture

ABSTRACT

In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable to higher-order multiplication. This multiplier topology is highly conducive for an electronic design automation (EDA) tool based implementation. A 32-bit version of this multiplier has been implemented using a standard ASIC design methodology and one variation of the standard design methodology in a 0.25μm technology. This 32-bit multiplier has a latency of 3.56ns.

REFERENCES

• 1: Hesham Al-Twaijry , Michael J. Flynn, Multipliers and Datapaths, Stanford University, Stanford, CA, 1994
• 2: L. Dadda. Some schemes for parallel multipliers. Alta Frequenza 34(5):349--356, March 1965.
• 3: M. Santoro. Design and clocking of vlsi multipliers. Ph. D. thesis, Stanford University October 1989.
• 4: C. Wallace. A suggestion for fast multipliers. IEEE Transactions on electronic Computers EC(13):14--17, February 1964.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design, Performance

Keywords:
CMOS VLSI, architecture, multiplier