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ABSTRACT
Routing is one of the most complex stages in the back-end design process. Simple routing algorithms based on two stages of global routing and detailed routing do not offer appropriate opportunities to address problems arising from signal delay, cross-talk and process constraints. An intermediate stage of track assignment between global and detailed routing proves to be an ideal place to address these problems. With this stage it is possible to use global routing information to efficiently address these problems and to aid the detailed router in achieving the wiring completions. In this paper we formulate routing as a three stage process; global routing, track assignment and detailed routing. We describe the intermediate track assignment problem and suggest an efficient heuristic for its solution. We introduce cost metrics to model basic effects arising from connectivity. We discuss extensions to include signal integrity and process constraints. We propose a heuristic based on weighted bipartite matching as a core routine. To improve its performance additional heuristics based on lookahead and segment splitting are also suggested. Experimental results are given to highlight the efficacy of track assignment stage in routing process.
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CITED BY 12
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Tsung-Yi Ho , Chen-Feng Chang , Yao-Wen Chang , Sao-Jie Chen, Multilevel full-chip routing for the X-based architecture, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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Yu-Ning Chang , Yih-Lang Li , Wei-Tin Lin , Wen-Nai Cheng, Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
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