ACM Home Page
Please provide us with feedback. Feedback
Track assignment: a desirable intermediate step between global routing and detailed routing
Full text pdf formatPdf (325 KB)
Source International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
Pages: 59 - 66  
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
Authors
Shabbir Batterywala  Synopsys Inc., Mountain View, CA
Narendra Shenoy  Synopsys Inc., Mountain View, CA
William Nicholls  Synopsys Inc., Mountain View, CA
Hai Zhou  Synopsys Inc., Mountain View, CA
Sponsors
: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 27,   Citation Count: 12
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues   peer to peer  

Tools and Actions: Review this Article  
Save this Article to a Binder    Display Formats: BibTex  EndNote ACM Ref   
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/774572.774581
What is a DOI?

ABSTRACT

Routing is one of the most complex stages in the back-end design process. Simple routing algorithms based on two stages of global routing and detailed routing do not offer appropriate opportunities to address problems arising from signal delay, cross-talk and process constraints. An intermediate stage of track assignment between global and detailed routing proves to be an ideal place to address these problems. With this stage it is possible to use global routing information to efficiently address these problems and to aid the detailed router in achieving the wiring completions. In this paper we formulate routing as a three stage process; global routing, track assignment and detailed routing. We describe the intermediate track assignment problem and suggest an efficient heuristic for its solution. We introduce cost metrics to model basic effects arising from connectivity. We discuss extensions to include signal integrity and process constraints. We propose a heuristic based on weighted bipartite matching as a core routine. To improve its performance additional heuristics based on lookahead and segment splitting are also suggested. Experimental results are given to highlight the efficacy of track assignment stage in routing process.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
H. B. Bakoglu, Circuits, interconnections, and packaging for VLSI, Addison-Wesley, Reading, MA, USA, 1990.
 
2
 
3
 
4
H.-P. Tseng, L. Scheffer, and C. Sechen, "Timing and crosstalk-driven area routing," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 20, no. 4, pp. 528--544, Apr. 2001.
5
 
6
 
7
C.-J. R. Shi, "Solving constrained via minimization by compact linear programming," Proceedings of the Asia and South Pacific Design Automation Conference, pp. 635--640, 1997.
 
8
C.-C. Chang and J. Cong, "An efficient approach to multilayer layer assignment with an application to via minimization," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 18, no. 5, pp. 608--620, May 1999.
 
9
 
10
J. M. Ho, M. Sarrafzadeh, G. Vijayan, and C. K. Wong, "Layer assignment for multichip modules," IEEE Trans. CAD, vol. 9, no. 12, pp. 1272--1277, December 1990.
 
11
M. J. Ciesielski, "Layer assignment for VLSI interconnect delay minimization," IEEE Trans. CAD, vol. 8, no. 6, pp. 701--707, June 1989.
 
12
P. Saxena and C. L. Liu, "Optimization of the maximum delay of global interconnects during layer assignment," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 20, no. 4, pp. 503--515, April 2001.
 
13
J. D. Cho, S. Raje, M. Sarrafzadeh, M. Sriram, and S. M. Kang, "Crosstalk-minimum layer assignment," Custom Integrated Circuits Conference, pp. 29.7.1--29.7.4, 1993.
14
15
 
16
P. Groeneveld and L. P. P. P. van Ginneken, "Method of designing a constraint-driven integrated circuit layout," U.S. Patent number 6,230,304, May 2001.
 
17
U. Gupta, D. T. Lee, and J. Leung, "An optimal solution for the channel assignment problem," IEEE Transactions on Computers, pp. 807--810, November 1979.
 
18
M. R. Garey, D. S. Johnson, G. L. Miller, and C. H. Papadimitrou, "The complexity of coloring circular arcs and chords," SIAM Journal on Algebraic Discrete Methods, vol. 1, no. 20, pp. 216--227, june 1980.
 
19
T. Yoshimura and E. S. Kuh, "Efficient algorithms for channel routing," IEEE Trans. CAD of Integrated Circuits and Systems, vol. CAD-1, no. 1, pp. 25--35, January 1982.
 
20
F. Harary, Graph Theory, Addison-Wesley, Reading, MA, USA, 1972.
 
21
 
22
 
23
M. Sarrafzadeh and D. T. Lee, "Restricted track assignment with application," International Journal of Computational Geometry and Applications, vol. 4, no. 1, pp. 53--68, 1994.

CITED BY  12
 
 
 
 

Collaborative Colleagues:
Shabbir Batterywala: colleagues
Narendra Shenoy: colleagues
William Nicholls: colleagues
Hai Zhou: colleagues

Peer to Peer - Readers of this Article have also read:
  • LR Parsing ACM Computing Surveys (CSUR)   6, 2
    A. V. Aho ,  S. C. Johnson