Transmission line design of clock trees

ABSTRACT

We investigate appropriate regimes for transmission line propagation of signals on digital integrated circuits. We start from exact solutions to the transmission line equations proposed by Davis and Meindl. We make appropriate modifications due to finite rise time. They affect the delay calculation and hypothesis pertaining the constancy of the electromagnetic parameters. We study these effects in detail. To find the domain of physical variables where transmission line behavior is feasible, we pose the problem as a nonlinear minimization problem in a space spanned by two continuous variables, with four parameters. From the resulting solutions and employing monotonicity properties of the functional we extract regimes of validity. These regimes of validity happen to be commensurate with what is reachable and doable with todays leading technologies. We complete this study with a qualitative analysis of driver insertion in the presence of transmission lines. The resulting configurations are suitable for the development of an improved clock design discipline.

REFERENCES

• 1: Y. L<sm>U</sm>, K. B<sm>ANERJEE AND</sm> M. C<sm>ELIK</sm>, A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance. CIS, Stanford University, 2001.
• 2: B. A. G<sm>IESEKE ET AL</sm>., A 600 MHz superscaler RISC microporcesor with out-of-order execution. Digest Tech. Papers 1997 Int. Solid-State Circuits Conf., pp. 176--177.
• 3: J. D<sm>AVIS AND</sm> J. M<sm>EINDL</sm>, Compact Distributed RLC Interconnect Models. IEEE Transactions on Electronic Devices, Vol. 47, No. 11, pp. 2068--2087, November 2000.
• 4: T. S<sm>AKURAI</sm>, Closed-forms expressions for interconnect delay, coupling, and crosstalk in VLSIs". IEEE Trans. Electron Devices, vol. 40, pp. 118--124, Jan. 1993.
• 5: R. M. A<sm>VERILL III ET AL</sm>., Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors. IBM, 1999.
• 6: N. C<sm>HANG ET AL</sm>., Clocktree RLC extraction with efficient Inductance modeling. IEEE Design Automation Conference (2000).
• 7: F. G<sm>ROVER</sm>, Inductance Calculations Working Formula and Tables. Instrument Society of America, 1945.
• 8: M. K<sm>AMON</sm>, M. J. T<sm>SUK, AND</sm> J. W<sm>HITE</sm>, FastHenry : A multiple-accelerated 3-D inductance extraction program. IEEE Trans. MTT, 42, no 9, Sept. 1994.
• 9: F. C<sm>HARLET ET AL</sm>., ICARE: A 3-D capacitance simulator. LETI, Grenoble, France.
• 10: Gene H. Golub , Victor Pereyra, The differentiation of pseudoinverses and nonlinear least squares problems whose variables separate., Stanford University, Stanford, CA, 1972
• 11: Yehea I. Ismail , Eby G. Friedman, Effects of inductance on the propagation delay and repeater insertion in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.2, p.195-206, April 2000 [doi>10.1109/92.831439 ]
• 12: K. B<sm>ANERJEE</sm>, A. M<sm>EHROTRA</sm>, Accurate Analisys of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling. IEEE Symposium on VLSI Circuits, Kyoto, Japan, June 14--16, 2001, pp. 195--198.
• 13: P. R<sm>ESTLE ET AL</sm>., A Clock Distribution Network for Microprocessors. IEEE Journal of Solid State Circuits, Vol. 36, No. 5, May, 2001, pp. 792--799.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Microprocessors and microcomputers

Additional Classification:
  G. Mathematics of Computing
  G.1 NUMERICAL ANALYSIS
      G.1.2 Approximation
          Subjects: Nonlinear approximation
      G.1.9 Integral Equations
          Subjects: Delay equations

General Terms:
Measurement, Standardization, Theory