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Efficient solution space exploration based on segment trees in analog placement with symmetry constraints
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Source International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
Pages: 497 - 502  
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
Authors
Florin Balasa  University of Illinois at Chicago
Sarat C. Maruvada  University of Illinois at Chicago
Karthik Krishnamoorthy  University of Illinois at Chicago
Sponsors
: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 9,   Downloads (12 Months): 16,   Citation Count: 5
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ABSTRACT

The traditional way of approaching devicelevel placement problems for analog layout is to explore a huge search space of absolute placement representations, where cells are allowed to illegally overlap during their moves [2, 7, 8]. This paper presents a novel analog placement technique operating on the set of binary tree representations of the layout [3], where the typical presence of an arbitrary number of symmetry groups of devices is directly taken into account during the exploration of the solution space. The efficiency of the novel approach is due to a data structure called segment tree, mainly used in computational geometry.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
F. Balasa, K. Lampaert, "Symmetry within the sequence-pair representation in the context of placement for analog design," IEEE Trans. CAD, Vol. 19, pp. 721--731, July 2000.
 
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K. Lampaert, G. Gielen, W. Sansen, "A performance-driven placement tool for analog integrated circuits" IEEE J. of Solid-State Circ., Vol. SC-30, No. 7, pp. 773--780, July 1995.
 
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E. Malavasi, E. Charbon, E. Felt, A. Sangiovanni-Vincentelli, "Automation of IC layout with analog constraints," IEEE Trans. CAD, Vol. 15, No. 8, pp. 923--942, Aug. 1996.
 
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H. Murata et al., "VLSI module placement based on rectangle-packing by the sequence-pair," IEEE Trans. CAD, Vol. 15, No. 12, pp. 1518--1524, Dec. 1996.
 
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S. Nakatake, K. Fujiyoshi, H. Murata, Y. Kajitani, "Module packing based on the BSG-structure and IC layout applications," IEEE Trans. CAD, Vol. 17, pp. 519--530, June 1998.
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Collaborative Colleagues:
Florin Balasa: colleagues
Sarat C. Maruvada: colleagues
Karthik Krishnamoorthy: colleagues

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