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Folding of logic functions and its application to look up table compaction
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Source International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
Pages: 694 - 697  
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
Authors
Shinji Kimura  Waseda University, 2-2 Hibikino 808-0135, Japan
Takashi Horiyama  Kyoto University, Kyoto, Japan
Masaki Nakanishi  Information Science, Nara Institute of Science and Technology, Takayama, Japan
Hirotsugu Kajihara  Information Science, Nara Institute of Science and Technology, Takayama, Japan
Sponsors
: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 24,   Citation Count: 1
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ABSTRACT

The paper describes the folding method of logic functions to reduce the size of memories for keeping the functions. The folding is based on the relation of fractions of logic functions. We show that the fractions of the full adder function have the bit-wise NOT relation and the bit-wise OR relation, and that the memory size becomes half (8-bit). We propose a new 3--1 LUT with the folding mechanisms whcih can implement a full adder with one LUT. A fast carry propagation line is introduced for a multi-bit addition. The folding and fast carry propagation mechanisms are shown to be useful to implement other multi-bit operations and general 4 input functions without extra hardware resources. The paper shows the reduction of the area consumption when using our LUTs compared to the case using 4--1 LUTs on several benchmark circuits.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
D. Buell et.al. Splash2: FPGAs in a Custom Computing Machine. IEEE Coputer Science Press, 1996.
 
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Varghese George and Jan M. Rabaey. Low Energy FPGA. Kluer Academic Publishers, 2001.
 
4
APEXII Programmable Logic Device Family Data Sheeet. Altera Corporation, 2000.
 
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Collaborative Colleagues:
Shinji Kimura: colleagues
Takashi Horiyama: colleagues
Masaki Nakanishi: colleagues
Hirotsugu Kajihara: colleagues

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