Dynamic hardware/software partitioning

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Dynamic hardware/software partitioning: a first approach

Full text

Pdf (215 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th conference on Design automation table of contents

Anaheim, CA, USA

SESSION: Issues in partitioning & design space eploration for codesign table of contents

Pages: 250 - 255

Year of Publication: 2003

ISBN:1-58113-688-9

Authors

Greg Stitt	University of California, Riverside
Roman Lysecky	University of California, Riverside
Frank Vahid	University of California, Riverside

Sponsor

ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 102, Citation Count: 29

Additional Information:

abstract references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTex EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/775832.775896 What is a DOI?

ABSTRACT

Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy consumption in embedded systems. Meanwhile, dynamic software optimization methods have shown the usefulness and feasibility of runtime program optimization, but those optimizations do not achieve as much as partitioning. We introduce a first approach to dynamic hardware/software partitioning. We describe our system architecture and initial on-chip tools, including profiler, decompiler, synthesis, and placement and routing tools for a simplified configurable logic fabric, able to perform dynamic partitioning of real benchmarks. We show speedups averaging 2.6 for five benchmarks taken from Powerstone, NetBench, and our own benchmarks.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Vasanth Bala , Evelyn Duesterwald , Sanjeev Banerjia, Dynamo: a transparent dynamic optimization system, Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation, p.1-12, June 18-21, 2000, Vancouver, British Columbia, Canada
	2	A. Balboni , W. Fornaciari , D. Sciuto, Partitioning and Exploration Strategies in the TOSCA Co-Design Flow, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.62, March 18-20, 1996
	3	D. Burger, T.M. Austin. The SimpleScalar Tool Set, Version 2.0. University of Wisconsin-Madison Computer Sciences Department Technical Report #1342, June 1997.
	4	P. Eles, Z. Peng, K. Kuchchinski, A. Doboli. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search. Kluwer's Design Automation for Embedded Systems, Vol. 2 No. 1, pp. 5--32, Jan. 1997.
	5	Rolf Ernst , Jorg Henkel , Thomas Benner, Hardware-Software Cosynthesis for Microcontrollers, IEEE Design & Test, v.10 n.4, p.64-75, October 1993 [doi>10.1109/54.245964 ]
	6	Excalibur, Altera Corp., http://www.altera.com.
	7	D.D. Gajski, F. Vahid, S. Narayan, J. Gong. SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm for Hardware/Software System Design. IEEE Transactions on VLSI Systems, Vol. 6, No. 1, pp. 84--100, 1998.
	8	Seth Copen Goldstein , Herman Schmit , Mihai Budiu , Srihari Cadambi , Matt Moe , R. Reed Taylor, PipeRench: A Reconfigurable Architecture and Compiler, Computer, v.33 n.4, p.70-77, April 2000 [doi>10.1109/2.839324 ]
	9	Michael Gschwind , Erik R. Altman , Sumedh Sathaye , Paul Ledak , David Appenzeller, Dynamic and Transparent Binary Translation, Computer, v.33 n.3, p.54-59, March 2000 [doi>10.1109/2.825696 ]
	10	Rajesh K. Gupta , Giovanni De Micheli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design & Test, v.10 n.3, p.29-41, July 1993 [doi>10.1109/54.232470 ]
	11	S. Hauck , T. W. Fry , M. M. Hosler , J. P. Kao, The Chimaera reconfigurable functional unit, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.87, April 16-18, 1997
	12	A. DeHon. DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century. Proc. FCCM, 1994.
	13	Jörg Henkel, A low power hardware/software partitioning approach for core-based embedded systems, Proceedings of the 36th ACM/IEEE conference on Design automation, p.122-127, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309896]
	14	Jouml;rg Henkel , Yanbing Li, Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder, Proceedings of the 6th international workshop on Hardware/software codesign, p.23-27, March 15-18, 1998, Seattle, Washington, United States
	15	Jörg Henkel , Rolf Ernst, A hardware/software partitioner using a dynamically determined granularity, Proceedings of the 34th annual conference on Design automation, p.691-696, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266323]
	16	Asawaree Kalavade , Edward A. Lee, A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem, Proceedings of the 3rd international workshop on Hardware/software co-design, September 22-24, 1994, Grenoble, France
	17	A. Klaiber. The Technology Behind Crusoe Processors. Transmeta Corporation White Paper, January 2000.
	18	A. Krall, Efficient JavaVM Just-in-Time Compilation, Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, p.205, October 12-18, 1998
	19	Afzal Malik , Bill Moyer , Dan Cermak, A low power unified cache architecture providing power and performance flexibility (poster session), Proceedings of the 2000 international symposium on Low power electronics and design, p.241-243, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344610]
	20	MIPS Technologies, Inc., http://www.mips.com.
	21	NetBench, http://cares.icsl.ucla.edu/NetBench/.
	22	Greg Stitt , Brian Grattan , Jason Villarreal , Frank Vahid, Using On-Chip Configurable Logic to Reduce Embedded System Software Energy, Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.143, September 22-24, 2002
	23	Greg Stitt , Frank Vahid, Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic, IEEE Design & Test, v.19 n.6, p.36-43, November 2002 [doi>10.1109/MDT.2002.1047742 ]
	24	Greg Stitt , Frank Vahid, Hardware/software partitioning of software binaries, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.164-170, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774596]
	25	Triscend Corporation, http://www.triscend.com, 2003.
	26	G. Vanmeerbeeck , P. Schaumont , S. Vernalde , M. Engels , I. Bolsens, Hardware/software partitioning of embedded system in OCAPI-xl, Proceedings of the ninth international symposium on Hardware/software codesign, p.30-35, April 2001, Copenhagen, Denmark [doi>10.1145/371636.371665]
	27	Virtex II Pro, Xilinx Corp., http://www.xilinx.com.
	28	M. Wan, Y. Ichikawa, D. Lidsky, J. Rabaey. An Energy Conscious Methodology for Early Design Exploration of Heterogeneous DSPs. Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, Santa Clara, pp. 111--117, May 1998.
	29	M. Wirthlin, B. Hutchings. DISC: The Dynamic Instruction Set Computer. FPGAs for Fast Board Development and Reconfigurable Computing. Proc. SPIE 2607, pp. 92--103, 1995.
	30	Xilinx Corporation, http://www.xilinx.com.

CITED BY 29

	Antonio Carlos S. Beck , Luigi Carro, Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Seraj Ahmad , Rabi N. Mahapatra, An efficient approach to on-chip logic minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.9, p.1040-1050, September 2007
	Antonio Carlos S. Beck , Victor F. Gomes , Luigi Carro, Exploiting Java through binary translation for low power embedded reconfigurable systems, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
	M. Singh, Memory access optimization of dynamic binary translation for reconfigurable architectures, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.1014-1020, November 06-10, 2005, San Jose, CA
	S. Ahmand , R. Mahapatra, M-trie: an efficient approach to on-chip logic minimization, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.428-435, November 07-11, 2004
	Roman Lysecky , Frank Vahid, On-chip logic minimization, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Madhura Purnaprajna , Marek Reformat , Witold Pedrycz, Genetic algorithms for hardware-software partitioning and optimal resource allocation, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.7, p.339-354, July, 2007
	G. Stiff , F. Vahid, New decompilation techniques for binary-level co-processor generation, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.547-554, November 06-10, 2005, San Jose, CA
	Roman Lysecky , Frank Vahid, A codesigned on-chip logic minimizer, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA
	Gaurav Mittal , David C. Zaretsky , Xiaoyong Tang , P. Banerjee, Automatic translation of software binaries onto FPGAs, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	David Zaretsky , Gaurav Mittal , Xiaoyong Tang , Prith Banerjee, Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Gaurav Mittal , David Zaretsky , Xiaoyong Tang , Prith Banerjee, An overview of a compiler for mapping software binaries to hardware, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.11, p.1177-1190, November 2007
	Greg Stitt , Frank Vahid , Gordon McGregor , Brian Einloth, Hardware/software partitioning of software binaries: a case study of H.264 decode, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Greg Stitt , Zhi Guo , Walid Najjar , Frank Vahid, Techniques for synthesizing binaries to an advanced register/memory structure, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Sankalp Kallakuri , Alex Doboli, Energy conscious online architecture adaptation for varying latency constraints in sensor network applications, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Zhi Guo , Walid Najjar , Frank Vahid , Kees Vissers, A quantitative analysis of the speedup factors of FPGAs over processors, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Roman Lysecky , Frank Vahid, A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning, Proceedings of the conference on Design, Automation and Test in Europe, p.18-23, March 07-11, 2005
	Roman Lysecky , Frank Vahid , Sheldon X.-D. Tan, Dynamic FPGA routing for just-in-time FPGA compilation, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Greg Stitt, Hardware/software partitioning with multi-version implementation exploration, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Roman Lysecky , Frank Vahid, A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning, Proceedings of the conference on Design, automation and test in Europe, p.10480, February 16-20, 2004
	Ann Gordon-Ross , Frank Vahid, Frequent loop detection using efficient non-intrusive on-chip hardware, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA
	Seng Lin Shee , Sri Parameswaran , Newton Cheung, Novel architecture for loop acceleration: a case study, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Ann Gordon-Ross , Frank Vahid, Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware, IEEE Transactions on Computers, v.54 n.10, p.1203-1215, October 2005
	Péter Arató , Zoltán Ádám Mann , András Orbán, Algorithmic aspects of hardware/software partitioning, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.136-156, January 2005
	M. Finc , A. Zemva, Profiling soft-core processor applications for hardware/software partitioning, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.5, p.315-329, May 2005
	Roman Lysecky , Greg Stitt , Frank Vahid, Warp Processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.659-681, July 2006
	Zoltán Ádám Mann , András Orbán , Péter Arató, Finding optimal hardware/software partitions, Formal Methods in System Design, v.31 n.3, p.241-263, December 2007
	Greg Stitt , Frank Vahid, Binary synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-30, August 2007
	Philip Garcia , Katherine Compton , Michael Schulte , Emily Blem , Wenyin Fu, An overview of reconfigurable hardware in embedded systems, EURASIP Journal on Embedded Systems, v.2006 n.1, p.13-13, January 2006