Microassembly and area reduction techniques for PLA microcode

Abstract

This paper presents new techniques for generating PLA microcode with the overall goal of implementing functions or algorithms in VLSI. The microcode is appropriate for PLA-based microarchitectures with powerful sequencing capabilities already proposed. A microassembly language is introduced with unusual flexibility for conditional field assembly and capability to support microarchitectures based on PLA stores An important contribution of this work is an area reduction algorithm for PLA microcode based on a breadth-first graph searching approach. Experimental results provided demonstrate the viability and usefulness of the proposed technique for designing PLA firmware in a VLSI environment.

References

1. 1 Brayton, R. et. al., "A Comparison of Logic Minimization Strategies using EXPRESSO: An APL Program Package for Partitioned Logic Minimization," Proceedings of the IEEE International Conference on Circuits and Computers, 1982.
2. 2 Chuquillanqui, S. and Perez-Segovia. T., "PAOLA: A Tool for Topological Optimization of Large PLAs," ACM IEEE Nineteenth Design Automation Conference Proceedings, pp. 300-306, 1982.
3. 3 Egan, J. and Liu, C., "Optimal Bipartite Folding of PLA," ACM IEEE Nineteenth Design Automation Conference Proceedings, pp. 141-146, 1982.
4. 4 Hatchel, G. et. al., "Techniques for Programmable Logic Array Folding," ACM IEEE Nineteenth Design Automation Conference Proceedings, pp. 147-155, 1982.
5. 5 Kang, S. and vanCleemput, W., "Automatic PLA Synthesis from a DDL-P Description," ACM IEEE Eighteenth Design Automation Conference Proceedings, pp. 391-397, 1981.
6. 6 Kernighan, B. and Ritchie, D., "The C Programming Language," Prentice Hall, 1978.
7. 7 Mick, J. and Brick, J., "Bit-Slice Microprocessor Design," McGraw Hill, 1980, pp. 168-175.
8. 8 Myers, G., "Digital System Design with LSI Bit-Slice Logic," John Wiley & Sons, 1980, pp. 300-322.
9. 9 Nilsson, N., "Principles of Artificial Intelligence," Tioga Publishing Company, 1980.
10. 10 Papachristou, C., "Hardware Microcontrol Schemes Using PLAs," Proc. 14th Annual IEEE Microprogramming Workshop, pp. 3-16, Dec. 1981.
11. 11 Papachristou, C. and Gambhir, S., "A Microsequencer Architecture with Firmware Support for Modular Microprogramming," Proc. 15th IEEE Microprogramming Workshop, pp. 105-113, Oct. 1982.
12. 12 Papachristou, C. and Gambhir, S., "A Bit-Slice Microcontrol Architecture for Structured Firmware Designs," IEEE 1983 International Workshop on Computer Systems Organization, pp. 154-163, March 1983.
13. 13 Reuter, J., "A Microassembler and PLA Compaction System for PLA Firmware," M.S. Thesis, University of Cincinnati, 1984.
14. 14 Ullman, J., "Computational Aspects of VLSI," Rockville, Maryland: Computer Science Press, 1984.

Index Terms

• Hardware

  • Electronic design automation

    • Logic synthesis

      • Circuit optimization

    • Methodologies for EDA

  • Integrated circuits

    • Logic circuits

      • Arithmetic and datapath circuits

      • Combinational circuits

      • Design modules and hierarchy

  • Very large scale integration design