skip to main content
article
Free Access

A model of interference in a shared resource multiprocessor

Authors Info & Claims
Published:17 January 1976Publication History
Skip Abstract Section

Abstract

This paper presents a generalized model of tightly-coupled multiprocessor systems which is then simplified to form a stochastic model for the study of interference. Analysis is performed on the resource contention which is characteristic of such systems in order to find a measure of system performance. After reviewing the problem of memory interference, the analysis is extended to contention in other individual resources, then combined to form a model for the interacting effects of contention in systems where processors contend for several shared resources.

References

  1. 1 Anderson, D. W., Sparacio, F. J. and Tomasulo, R. M. "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling" IBM J. of R. & D. 11:1 (Jan. 1967), pp. 8-24.Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2 Bell, C. G. and Newell, A. Computer Structures: Readings and Examples McGraw-Hill, New York, N. Y., 1971. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. 3 Bhandarkar, D. P. "Analytic Models for Memory Interference in Multiprocessor Computer Systems" Ph.D. Dissertation, Carnegie-Mellon University, Sept. 1973. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4 Flynn, M. J. and Podvin, A. "An Unconventional Computer Architecture: Shared Resource Multiprocessing" Computer 5:2 (March-Apr. 1972), pp. 20-28.Google ScholarGoogle Scholar
  5. 5 Gountanis, R. J. and Viss, N. L. "A Method of Processor Selection for Interrupt Handling in a Multiprocessor System" Proc. IEEE 54:12 (Dec. 1966) pp. 1812-1819.Google ScholarGoogle ScholarCross RefCross Ref
  6. 6 Jensen, J. E. "Dynamic Task Scheduling in a Shared Resource Multiprocessor" Ph.D. Dissertation, University of Washington (in preparation). Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. 7 Pariser, J. J. "Multiprocessing With Floating Executive Control" IEEE Int. Conv. Record, 1965, pp. 266-275.Google ScholarGoogle Scholar
  8. 8 Skinner, C. E. and Asher, J. R. "Effects of Storage Contention on System Performance" IBM Systems J. 8:4 (1969), pp. 319-333.Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. 9 Strecker, W. D. "Analysis of the Instruction Rate in Certain Computer Structures" Ph.D. Dissertation, Carnegie-Mellon University, June 1970. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. 10 Watson, W. J. "The TI ASC—A Highly Modular and Flexible Super Computer Architecture" Proc. AFIPS 1972 F.J.C.C., pp. 221-228.Google ScholarGoogle Scholar
  11. 11 Wulf, W. A. and Bell, C. G. "C.mmp—A Multi-Mini-Processor" Proc. AFIPS 1972 F.J.C.C., pp. 765-777.Google ScholarGoogle Scholar

Index Terms

  1. A model of interference in a shared resource multiprocessor

          Recommendations

          Comments

          Login options

          Check if you have access through your login credentials or your institution to get full access on this article.

          Sign in

          Full Access

          • Published in

            cover image ACM SIGARCH Computer Architecture News
            ACM SIGARCH Computer Architecture News  Volume 4, Issue 4
            January 1976
            210 pages
            ISSN:0163-5964
            DOI:10.1145/633617
            Issue’s Table of Contents

            Copyright © 1976 Authors

            Publisher

            Association for Computing Machinery

            New York, NY, United States

            Publication History

            • Published: 17 January 1976

            Check for updates

            Qualifiers

            • article

          PDF Format

          View or Download as a PDF file.

          PDF

          eReader

          View online with eReader.

          eReader