Takashi Mitsuhashi
ABSTRACT
A new LSI artwork analysis and processing system, called EMAP, is described with algorithms, a database schema and applications. EMAP provides the designer with the artwork verification and processing tools which include mask artwork processing, geometrical design rule checking, connectivity analysis and electrical circuit parameter calculation. The circuit connectivity data derived from the mask artwork data is used for input to a logic simulator, a timing simulator, a circuit simulator and a circuit schematic generator.
- 1.K. Kani, A. Yamada and M. Teramoto, "CAD in The Japanese Electronic Industry" Symp. on CAD of Digital Electronic Circuits and Systems, Brussels, pp. 115-131 (Nov. 1978).Google Scholar
- 2.B. W. Lindsay and B. T. Preas, "Design Rule Checking and Analysis of IC Mask Design", Proc. 13th Design Automation Conference, pp. 301-308 (June 1976). Google ScholarDigital Library
- 3.H. S. Baird, "Fast Algorithms for LSI Artwork Analysis", Proc. 14th Design Automation Conference, pp. 303-311 (June 1977). Google ScholarDigital Library
- 4.K. Yoshida, T. Mitsuhashi, Y. Nakada, T. Chiba, K. Ogita and S. Nakatsuka, "A Layout Checking System for Large Scale Integrated Circuits", Proc. 14th Design Automation Conference, pp. 322-330 (June 1977). Google ScholarDigital Library
- 5.P. Wilcox, H. Rombeek and D. M. Caughey, "Design Rule Verification Basen on One Dimensional Scans", Proc. 15th Design Automation Conference, pp. 285-289 (June 1978). Google ScholarDigital Library
- 6.H. S. Baird and Y. E. Cho, "An Artwork Design Verification System", Proc. 12th Design Automation Conference, pp. 414-420 (June 1975). Google ScholarDigital Library
- 7.B. T. Preas, B. W. Lindsay and C. W. Gwyn, "Automatic Circuit Analysis Based on Mask Information", Proc. 13th Design Automation Conference, pp. 309-317 (June 1976). Google ScholarDigital Library
- 8.C. R. McCaw, "Unified Shapes Checker - A Cheking Tool for LSI", Proc. 16th Design Automation Conference, pp. 81-87 (June 1979). Google ScholarDigital Library
- 9.C.S. Chang, "LSI Layout Checking Using Bipolar Device Recognition Technique", Proc. 16th Design Automation Conference, pp. 95-101 (June 1979). Google ScholarDigital Library
- 10.P. Losleben and K. Tompson, "Topological Analysis for VLSI Circuits", Proc. 16th Design Automation Conference, pp. 461-473 (June 1979). Google ScholarDigital Library
- 11.K. Hirabayashi and M. Kawamura, "MACLOS - A Mask Checking Logic Simulator" (to appear).Google Scholar
- 12.M. Kawamura and K. Hirabayashi, "MACTIS - A Mask Checking Timing Simulator" (to appear).Google Scholar
- 13.A. V. Aho, J. E. Hopcroft and J. D. Ullman "The Design and Analysis of Computer Algorithms", Addison-Wesley, Reading, 1974. Google ScholarDigital Library
- 14."CODASYL Data Description Language Journal of Development June, 1973".Google Scholar
Index Terms
- An integrated mask artwork analysis system
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