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F/LOGIC - An interactive fault and logic simulator for digital circuits

Published:28 June 1976Publication History

ABSTRACT

Digital simulators are becoming a standard and necessary CAD tool in the circuit design process. The acceptance of this design aid is a result of a number of factors, the predominant one being the over-whelming size and complexity of present day logic circuits and the requirement that a complete test plan be developed for these circuits. Another factor is that recent generation logic simulators have proven to be very flexible tools, capable of simulating very large circuits with a high degree of precision.

References

  1. 1.M. J. Flomenhoft, B. M. Csencsits, 'A Minicomputer - Based Logic Circuit Fault Simulator', Proc. 11th ACM Design Automation Workshop, Denver, 1974. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2.S. A. Szygenda, 'TEGAS2-Anatomy of a General Purpose Test Generation and Simulation System for Digital Logic', PROC. of the 9th ACM Design Automation Workshop, June 1972. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. 3.M. A. Breuer, 'A Note on Three-Valued Logic Simulation', IEEE Trans. on Computers, C-21 page 399, Apr. 14, 1972.Google ScholarGoogle Scholar
  4. 4.S. A. Szygenda and E. W. Thompson, 'Digital Logic Simulation in a Time-Based, Table-Driven Environment', IEEE Computer Magazine, pp. 24-48, March 75. Google ScholarGoogle ScholarDigital LibraryDigital Library

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  1. F/LOGIC - An interactive fault and logic simulator for digital circuits

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            cover image ACM Conferences
            DAC '76: Proceedings of the 13th Design Automation Conference
            June 1976
            512 pages

            Copyright © 1976 ACM

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            Association for Computing Machinery

            New York, NY, United States

            Publication History

            • Published: 28 June 1976

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