Partitioning and ordering of logic equations for optimum MOS LSI device layout

ABSTRACT

The concepts underlying a versatile tiered layout design scheme for MOS LSI logic devices is presented. A series of three computer-aided design programs is discussed which provide designers with information permitting rapid organization of minimum area layout designs.

References

1. 1.R. P. Larsen, "Computer-Aided Preliminary Layout Design of Customized MOS Arrays", IEEE Trans. on Computers, Vol. C-20, No. 5, May 1971.
2. 2.A. Weinberger, "Large Scale Integration of MOS Complex Logic; A Layout Method", IEEE Journal on Solid-State Circuits, Vol. SC-2, No. 4, December 1967, pp. 182-190.