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T3: Trends and Challenges in VLSI Technology Scaling towards 100nm

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with EDA Technofair Design Automation Conference Asia and South Pacific archive
Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design table of contents

Page: 16

Year of Publication: 2002

ISBN:0-7695-1441-3

Authors

S. Rusu	Intel Corporation
M. Sachdev	University of Waterloo, Canada
C. Svensson	Linkoping University, Sweden
B. Nauta	University of Twente, The Netherlands

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 33, Citation Count: 1

Additional Information:

cited by collaborative colleagues peer to peer

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CITED BY

Serkan Ozdemir , Arindam Mallik , Ja Chun Ku , Gokhan Memik , Yehea Ismail, Variable latency caches for nanoscale processor, Proceedings of the 2007 ACM/IEEE conference on Supercomputing, November 10-16, 2007, Reno, Nevada

Collaborative Colleagues:

S. Rusu: colleagues

M. Sachdev: colleagues

C. Svensson: colleagues

B. Nauta: colleagues

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