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IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium®-based systems
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Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture table of contents
Page: 191  
Year of Publication: 2003
ISBN:0-7695-2043-X
Authors
Sponsor
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society  Washington, DC, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 30,   Citation Count: 17
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ABSTRACT

IA-32 Execution Layer (IA-32 EL) is a newtechnology that executes IA-32 applications onIntel® Itanium® processor family systems.Currently, support for IA-32 applications onItanium-based platforms is achieved usinghardware circuitry on the Itanium processors.This capability will be enhanced with IA-32EL-software that will ship with Itanium-basedoperating systems and will convert IA-32instructions into Itanium instructions viadynamic translation.In this paper, we describeaspects of the IA-32 Execution Layertechnology, including the general two-phasetranslation architecture and the usage of asingle translator for multiple operatingsystems.The paper provides details of someof the technical challenges such as preciseexception, emulation of FP, MMXTM, and Intel®Streaming SIMD Extension instructions, andmisalignment handling.Finally, the paperpresents some performance results.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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[1] Eric R. Altman, Kemal Ebcioglu, Michael Gschwind and Sumedh Sathaye, "Advances and Future Challenges in Binary Translation and Optimization", Proceedings of the IEEE Special Issue on Microprocessor Architecture and Compiler Technology, November 2001.
 
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[8] Paul J. Drongowski, David Hunter, Morteza Fayyazi, David Kaeli, "Studying the Performance of the FX!32 Binary Translation System", in the Proceedings of the 1st Workshop on Binary Translation, Newport Beach, CA, Oct. 1999.
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[12] Intel Corporation, "Intel IA-32 Architecture Software Developer's Manual", Vol. 1-3 2003.
 
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[13] Intel Corporation, "Intel IA-64 Architecture Software Developer's Manual", Vol. 1-4, January 2000.
 
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[14] Michael Gschwind and Eric R. Altman, "Optimizing and Precise Exceptions in Dynamic Compilation", Second Workshop on Binary Translation Held in PACT 2000.
 
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[17] S.J. Patel and S.S. Lurnetta. "Replay: A Hardware Framework for Dynamic Program Optimization", Technical Report CRHC-99-16, University of Illinois, December 1999.
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[19] Intel compilers http://wwww.intel.com/software/products/compilers/
 
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[20] SPEC CPU2000 http://www.specbench.org/osg/cpu2000
 
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[21] Sum Microsystems, "The Java Hotspot Performance Engine Architecture", http://java.sun.com/products/hotspot/whitepaper.ht ml, April 1999.
 
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[22] David Ung and Cristina Cifuentes, "Optimizing Hot Paths in a Dynamic Binary Translator", Second Workshop on Binary Translation Held in PACT 2000, October 2000.
 
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CITED BY  17
 
 
 
 
 
 
 
 
 

Collaborative Colleagues:
Leonid Baraz: colleagues
Tevi Devor: colleagues
Orna Etzion: colleagues
Shalom Goldenberg: colleagues
Alex Skaletsky: colleagues
Yun Wang: colleagues
Yigel Zemach: colleagues

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