Cristian Grecu
ABSTRACT
Multi-Processor (MP-SoC) platforms are emerging as the latest trend in SoC design. Monolithic bus-based interconnect architectures will not be able to support the clock cycle requirements of these high performance SoCs. Systems having multiple smaller buses, integrated through repeaters or bridges, are possible alternatives. But these kinds of solutions are ad-hoc in nature. By adopting a more structured network-based design paradigm, specific clock cycle requirements can easily be met. The precise focus of this paper is to show how the butterfly fat tree (BFT) can meet this objective when used as the overall MP-SoC interconnect architecture, thereby offering an attractive alternative for SoC interconnect that does not suffer from the non-scalability aspect of the buses in regards to the clock cycle.
- P. Magarshack, P.G. Paulin, "System-on-Chip Beyond the Nanometer Wall", Proceedings of DAC'03, June 2-6,2003, Anaheim, USA. Google Scholar
Digital Library
- M.A. Horowitz, et al., "The Future of Wires", Proceedings of the IEEE, Volume: 89 Issue: 4, April 2001 pp. 490-504.Google Scholar
- K. C. Saraswat, et al., "Technology and Reliability Constrained Future Copper Interconnects - Part II: Performance Implications," IEEE Transactions on Electron Devices, Vol. 49, No. 4, April 2002 pp. 598--604.Google ScholarCross Ref
- Y. Zorian, "Guest editor's introduction: what is infrastructure IP?", IEEE Design & Test of Computers, Volume: 19 Issue: 3 , May-June 2002 pp. 3--5. Google ScholarDigital Library
- D. Wingard, " MicroNetwork-Based Integration for SoCs", Proc. DAC 2001, pp. 673-677, Las Vegas, Nevada, USA, June 18-22, 2001. Google ScholarDigital Library
- Open Core Protocol, www.ocpip.org.Google Scholar
- MIPS SoC-it, www.mips.com.Google Scholar
- S. Kumar, et al, " A Network on Chip Architecture and Design Methodology," Proceedings of ISVLSI, pp. 117--124, 2002. Google ScholarDigital Library
- W. J. Dally, and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks", Proceedings of DAC 2001, pp. 683-689, Las Vegas, Nevada, USA, June 18-22, 2001. Google ScholarDigital Library
- I. Saastamoinen, et al, "Interconnect IP Node for Future System-on-Chip Designs", Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications, pp. 116--120, 2002. Google ScholarDigital Library
- P. Guerrier, A. Greiner, "A generic architecture for on-chip packet-switched interconnections", Proceedings of Design, Automation and Test in Europe Conference and Exhibition 2000, pp. 250--256. Google ScholarDigital Library
- P. P. Pande, C. Grecu, A. Ivanov, R. Saleh, "Design of a Switch for Network on Chip Applications", Proceedings of ISCAS, Bangkok, May 2003.Google Scholar
- P. P. Pande, C. Grecu, A. Ivanov, R. Saleh, "High-Throughput Switch-Based Interconnect for Future SoCs", Proceedings of 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, June 30-July 2, 2003, Calgary, Canada.Google Scholar
- D. Sylvester, K. Keutzer, "Impact of Small Process Geometries on Microarchitectures in Systems on a Chip", Proceedings of the IEEE, Vol. 89, No. 4, April 2001, pp. 467--489.Google ScholarCross Ref
- Design and Reuse website, http://www.us.design-reuse.com/sip/.Google Scholar
- C. E. Leiserson, "Fat Trees: Universal networks for hardware efficient supercomputing". IEEE Transactions on Computers, C-34 (10): pp. 892--901. Oct. 1985. Google ScholarDigital Library
- ITRS 2002 Documents, http://public.itrs.net/Files/2002Update/Home.pdf.Google Scholar
- D. A. Hodges, H. G. Jackson and R. Saleh, Analysis and Design of Digital Integrated Circuits, Third Edition, McGraw-Hill, 2003. Google ScholarDigital Library
- Cristian Grecu, Partha Pratim Pande, Andre Ivanov, Res Saleh, "A Scalable Communication-Centric SoC Interconnect Architecture," IEEE International Symposium on Quality Electronic Design, ISQED 2004 San Jose, California, USA, 22-24 March, 2004. Google ScholarDigital Library
- I. Sutherland, B. Sproull and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann, 1999. Google ScholarDigital Library
Index Terms
- Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs
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