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Cluster miss prediction for instruction caches in embedded networking applications

Published:26 April 2004Publication History

ABSTRACT

In this paper, we describe a new method of instruction prefetching that reduces the cache miss penalty by anticipating the cache behavior based on previous execution. Our observations indicate that instruction cache misses often repeat in clusters under certain conditions prevalent in real time embedded networking systems. By identifying the start of a cluster miss sequence and preparing an instruction buffer for the upcoming cache misses, the miss penalty can be reduced if a miss does occur. A sample industrial networking example is used to illustrate the effectiveness of this technique compared with other prefetch methods.

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              cover image ACM Conferences
              GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI
              April 2004
              479 pages
              ISBN:1581138539
              DOI:10.1145/988952

              Copyright © 2004 ACM

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              • Published: 26 April 2004

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