| An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512) |
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Great Lakes Symposium on VLSI
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Proceedings of the 14th ACM Great Lakes symposium on VLSI
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Boston, MA, USA
POSTER SESSION: Poster session 2
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Pages: 421 - 425
Year of Publication: 2004
ISBN:1-58113-853-9
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Authors
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Luigi Dadda
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Politecnico di Milano, Milan, Italy and ALaRI-USI, Lugano, Switzerland
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Marco Macchetti
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Politecnico di Milano, Milan, Italy
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Jeff Owen
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STMicroelectronics NV, Manno, Switzerland
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Downloads (6 Weeks): 11, Downloads (12 Months): 72, Citation Count: 1
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ABSTRACT
An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13um technology.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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NIST. Announcing the secure hash standard. Federal Information Processing Satndards Publication 180-2, August 2002.
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Y. K. Kang, D. W. Kim, T. W. Kwon, and J. R. Choi. An efficient implementation of hash function processor for ipsec. Proceedings of the 3rd Asia-Pacific Conference on ASICs, August 2002.
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Tim Grembowski , Roar Lien , Kris Gaj , Nghi Nguyen , Peter Bellows , Jaroslav Flidr , Tom Lehman , Brian Schott, Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512, Proceedings of the 5th International Conference on Information Security, p.75-89, September 30-October 02, 2002
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N. Sklavos and O. Koufopavlou. On the hardware implementations of the sha-2(256,384,512) hash functions. Proc. of ISCAS 2003, May 2003.
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