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An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 14th ACM Great Lakes symposium on VLSI table of contents
Boston, MA, USA
POSTER SESSION: Poster session 2 table of contents
Pages: 421 - 425  
Year of Publication: 2004
ISBN:1-58113-853-9
Authors
Luigi Dadda  Politecnico di Milano, Milan, Italy and ALaRI-USI, Lugano, Switzerland
Marco Macchetti  Politecnico di Milano, Milan, Italy
Jeff Owen  STMicroelectronics NV, Manno, Switzerland
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 11,   Downloads (12 Months): 72,   Citation Count: 1
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ABSTRACT

An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13um technology.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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NIST. Announcing the secure hash standard. Federal Information Processing Satndards Publication 180-2, August 2002.
 
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Y. K. Kang, D. W. Kim, T. W. Kwon, and J. R. Choi. An efficient implementation of hash function processor for ipsec. Proceedings of the 3rd Asia-Pacific Conference on ASICs, August 2002.
 
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N. Sklavos and O. Koufopavlou. On the hardware implementations of the sha-2(256,384,512) hash functions. Proc. of ISCAS 2003, May 2003.
 
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Collaborative Colleagues:
Luigi Dadda: colleagues
Marco Macchetti: colleagues
Jeff Owen: colleagues

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