Article

Design and CAD Challenges in sub-90nm CMOS Technologies

Authors:

Kerry Bernstein,

Ching-Te Chuang,

Ruchir PuriAuthors Info & Claims

ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Page 129

Published: 09 November 2003 Publication History

Abstract

This paper discusses design challenges of scaled CMOS circuits insub-90nm technologies for high-performance digital applications.To continue scaling of the CMOS devices deep into sub-90nm tech-nologies,fully depleted SOI, strained-Si on SiGe, FinFETs withdouble gate, and even further, three-dimensional circuits will be uti-lizedto design high-performance circuits. We will discuss uniquedesign aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process vari-ations.As the scaling approaches various physical limits, new SOIdesign issues such as Vt modulation due to leakage, low-voltageimpact ionization, and higher V{t,lin} to maintain adequate V{t,sat},continue to surface.With an eye towards the future, design andCAD issues related to sub-65nm device structures such as doublegate FinFET will be discussed.

References

[1]

{1} C. T. Chuang et al. "SOI for digital CMOS VLSI: design considerations and advances," Proc. IEEE, vol. 86, no. 4, April 1998.

[2]

{2} C. T. Chuang and R. Puri, "SOI digital CMOS VLSI - a design perspective," Design Automation Conf., 1999, pp. 709-714.

Digital Library

[3]

{3} K. Bernstein, et al, "SOI Circuit Design Concepts", Kluwer Academic Publishers, February, 2000.

Digital Library

[4]

{4} K. L. Shepard et al., "Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis," ICCAD, 1999.

Digital Library

[5]

{5} D. Lee, et al., "Analysis and Minimization Techniques for total Leakage Considering Gate Oxide Leakage," Design Automation Conf., 2003.

Digital Library

[6]

{6} S. R. Nassif et al., "SOI Technology and Tools," ICCAD, 1999.

Digital Library

[7]

{7} K Rim, et al., "Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs," Symp. VLSI Technology, 2002, pp. 98-99.

[8]

{8} J. Kedzierski, et al., "High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices", IEDM, 2001, p. 19.5.1.

[9]

{9} T. Ghani, et al., "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," Symp. VLSI Technology, 2000, pp. 174-175.

[10]

{10} W. C. Lee and C. Hu, "Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling," Symp. VLSI Technology, 2000, pp. 198-199.

[11]

{11} S. K. H. Fung, et al., "Controlling floating-body effects for 0.13 µm and 0.10 µm SOI CMOS," IEDM, 2000, pp. 231-234.

[12]

{12} C. T. Chuang, R. Puri, and K. Bernstein, "Effect of gate-to-body tunneling current on PD/SOI CMOS circuits," Int'l Conf. on Solid State Devices and Materials, Tokyo, Japan, 2001, pp. 262-263.

[13]

{13} C. T. Chuang and R. Puri, "Effects of gate-to-body tunneling current on pass-transistor based PD/SOI CMOS circuits," Proc. IEEE Int'l SOI Conf., 2002, pp. 121-122.

[14]

{14} C. T. Chuang and R. Puri, "Effects of gate-to-body tunneling current on PD/SOI CMOS Latches," Submitted to Conference on Simulation of Semiconductor Processes and Devices (SISPAD'03), 2003.

[15]

{15} R. V. Joshi, et al., "Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM," Symp. VLSI Technology, 2001, pp. 75-76.

[16]

{16} H. Wan, et al., "Tendency of full depletion due to gate tunneling current," Proc. IEEE Int'l SOI Conf., 2002, pp. 140-141.

[17]

{17} R. V. Joshi, et al., "3D thermal analysis for SOI and its impact on circuit performance," Proc. International Conf. on Simulation of Semiconductor Processes and Devices (SISPAD'01), 2001, pp. 242-245.

[18]

{18} M. Ashegi, et al., "Thermal conductivity model for thin silicon-on-insulator layers at high temperatures," Proc. IEEE Int'l SOI Conf., 2002, pp. 51-52.

[19]

{19} C. Hu, et al., "Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement", IEEE Transactions on Electron Devices, Vol. ED32, No. 2, pp. 375-382, February, 1985.

[20]

{20} A.M. Yassine, et al., "Time dependent breakdown of ultrathin gate oxide", Electron Devices, IEEE Transactions on, Volume: 47 Issue: 7, Jul 2000, Page(s): 1416-1420.

[21]

{21} K. Bernstein, et al, "High Speed Circuit Design Styles", Chapter 1, Kluwer Academic Publishers, January, 1998.

[22]

{22} V. Reddy, et al., "Impact of negative bias temperature instability on digital circuit reliability", Reliability Physics Symposium Proceedings, 2002. 40th Annual, 2002, Page(s): 248-254.

[23]

{23} P. F. Lu, et al., "Floating body effects in partially-depleted SOI CMOS circuits," IEEE J. Solid-State Circuits, vol. 32, no. 8, August 1997, pp. 1241-1253.

[24]

{24} C. T. Chuang, et al., "Dual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially-depleted SOI devices," Proc. Tech. Papers, Int'l Symp. on VLSI Tech., Syst., and Applications, Taipei, Taiwan, 1997, pp. 288-292.

[25]

{25} M. Canada, et al., "A 580MHz RISC microprocessor in SOI," ISSCC, 1999, pp. 430-431.

[26]

{26} D. H. Allen, et. al., "A 0.20 µm 1.8 V SOI 550MHz 64b PowerPC microprocessor with Cu interconnects," ISSCC, 1999, pp. 438-439.

[27]

{27} J. B. Kuang, et al., "A dynamic body discharge technique for SOI circuit applications," Proc. IEEE Int'l SOI Conf., 1999, pp. 77-78.

[28]

{28} J. B. Kuang, D. H. Allen, and C. T. Chuang, "Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology," IEEE J. Solid-State Circuits, vol. 36, no. 4, April 2001, pp. 597-604.

[29]

{29} J. B. Kuang and C. T. Chuang, "A tri-state body charge modulated SOI sense amplifier," Proc. IEEE Int'l SOI Conf., 2001, pp. 135-136.

[30]

{30} A. Wei, et al., "Minimizing floating-body-induced threshold voltage variation in partially depleted SOI CMOS," IEEE Elec. Dev. letters, vol. 17, no. 8, Aug. 1996, pp. 391-394.

[31]

{31} A. Wei and D. Antoniadis, "Design methodology for minimizing hysteretic V_t -variation in partially-depleted SOI CMOS," IEDM, 1997, pp. 411-414.

[32]

{32} T. W. Houston and S. Unnikrishnan, "A guide to simulation of hysteretic gate delays based on physical understanding," Proc. IEEE Int'l SOI Conf., 1998, pp. 121-122.

[33]

{33} M. M. Pelella, et al., "Hysteresis in floating-body PD/SOI CMOS circuits," Symp. on VLSI Tech., Syst., and Applications, Taipei, Taiwan, 1999, pp. 278-281.

[34]

{34} R. Puri and C. T. Chuang, "Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits," Proc. IEEE Int'l SOI Conf., 1998, pp. 103-104.

[35]

{35} R. Puri and C. T. Chuang, "Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits," Proc. Int'l Symp. on Low Power Electronics and Design, 1999, pp. 223-228.

Digital Library

[36]

{36} K. A. Jenkins, R. Puri, C. T. Chuang, and F. L. Pesavento, "Measurement of history effect in PD/SOI single-ended CPL circuit," Proc. IEEE Int'l SOI Conf., 2001, pp. 57-58.

[37]

{37} I. Aller and K. E. Kroell, "Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits," Proc. IEEE Int'l SOI Conf., 1999, pp. 40-41.

[38]

{38} P. Su, et al., "Self-heating enhanced impact ionization in SOI MOSFETs," Proc. IEEE Int'l SOI Conf., 2001, pp. 31-32.

[39]

{39} P. Su, et al., "An impact ionization model for SOI circuit simulation," Proc. IEEE Int'l SOI Conf., 2002, pp. 201-202.

[40]

{40} E. Leobandung, et al., "Scalability of SOI technology into 0.13 µm 1.2 V CMOS generation," IEDM, 1998, pp. 403-406.

[41]

{41} K. Rim, "Strained Si surface channel MOSFETs for high-performance CMOS technology," ISSCC, 2001, pp. 116-117.

[42]

{42} L. J. Huang, et al., "Carrier mobility enhancement in strained Sion-insulator fabricated by wafer bonding," Symp. VLSI Technology, 2001, pp. 57-58.

[43]

{43} K. Kim, et al., "Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS device/circuit," Proc. IEEE Int'l SOI Conf., 2002, pp. 17-19.

[44]

{44} D. Matzke, "Will physical scalability sabotage performance gains?", Computer, Volume: 30 Issue: 9, Sep 1997, Page(s): 37-39.

Digital Library

[45]

{45} K. Guarini, et al., "The Impact of Wafer Level Layer Transfer on High Performance Devices and Circuits for 3D IC Fabrication", ECS, Paris France, May 2003.

[46]

{46} M. Reed, et al., "Computing with Molecules", Scientific American, June, 2000.

Cited By

Singh HRao RAgarwal KSylvester DBrown R(2010)Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noiseIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203129018:1(166-170)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2031290
Mishra PMuttreja AJha N(2009)Low-power FinFET circuit synthesis using multiple supply and threshold voltagesACM Journal on Emerging Technologies in Computing Systems10.1145/1543438.15434405:2(1-23)Online publication date: 16-Jul-2009
https://dl.acm.org/doi/10.1145/1543438.1543440
Swahn BHassoun S(2008)Electro-thermal analysis of multi-fin devicesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200045516:7(816-829)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2000455
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Index Terms

Design and CAD Challenges in sub-90nm CMOS Technologies
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Integrated circuits
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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Published In

cover image ACM Conferences

ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

November 2003

899 pages

ISBN:1581137621

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society

United States

Publication History

Published: 09 November 2003

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ICCAD03

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ICCAD03: The International Conference on Computer-Aided Design

November 9 - 13, 2003

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ICCAD '03 Paper Acceptance Rate 129 of 490 submissions, 26%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Singh HRao RAgarwal KSylvester DBrown R(2010)Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noiseIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203129018:1(166-170)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2031290
Mishra PMuttreja AJha N(2009)Low-power FinFET circuit synthesis using multiple supply and threshold voltagesACM Journal on Emerging Technologies in Computing Systems10.1145/1543438.15434405:2(1-23)Online publication date: 16-Jul-2009
https://dl.acm.org/doi/10.1145/1543438.1543440
Swahn BHassoun S(2008)Electro-thermal analysis of multi-fin devicesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200045516:7(816-829)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2000455
Singh HAgarwal KSylvester DNowka K(2007)Enhanced leakage reduction techniques using intermediate strength power gatingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1376080.137608415:11(1215-1224)Online publication date: 1-Nov-2007
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Medardoni SBertozzi DMacii EMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologiesProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283815(159-164)Online publication date: 27-Aug-2007
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Fazzi AMagagni LDe Dominicis MZoffoli PCanegallo RRolandi PSangiovanni-Vincentelli AGuerrieri RHassoun S(2006)Yield prediction for 3D capacitive interconnectionsProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233667(809-814)Online publication date: 5-Nov-2006
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Frank DPuri RToma DHassoun S(2006)Design and CAD challenges in 45nm CMOS and beyondProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233567(329-333)Online publication date: 5-Nov-2006
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Swahn BHassoun SSentovich E(2006)Gate sizingProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147047(528-531)Online publication date: 24-Jul-2006
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Agarwal KNowka KDeogun HSylvester D(2006)Power Gating with Multiple Sleep ModesProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.102(633-637)Online publication date: 27-Mar-2006
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