Many embedded system designs usually impose (hard)read-time constraints on tasks. Thus, computing a tight upper boundof the worst case execution time (WCET) of a software is a criticallyimportant, but difficult task. The difficulty arises particularlywhen the code is executed on processors with cache-based memorysystems. In this paper, we propose a new code placement techniqueunder cache activity consideration for real-time software design.Specifically, unlike the previous approaches which have triedto minimize total cache misses, which is not necessarily the bestway to meet all timing constraints of tasks, we minimizes the cachemisses in a selective way for tasks according to the degree of tightness(or urgency) of their timing constraints. Based on a concept ofselective cache activity minimization, we propose a new approachwhich solves the code placement problem in two steps: (Step 1) Wetransform the code placement problem into so called an interval selectionproblem, which then we formulate into a 0-1 integer linearprogramming (ILP); (Step 2) We apply an efficient approximationalgorithm, called Code-map, to solve the exact code placementformulation obtained in Step.