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Analytical Bound for Unwanted Clock Skew due to Wire Width Variation

Published: 09 November 2003 Publication History

Abstract

Under modern VLSI technology, process variations greatly affectcircuit performance, especially clock skew which is very timingsensitive. Unwanted skew due to process variation forms a bottleneckpreventing further improvement on clock frequency. Impactfrom intra-chip interconnect variation is becoming remarkable andis difficult to be modeled efficiently due to its distributive nature.Through wire shaping analysis, we establish an analytical boundfor the unwanted skew due to wire width variation which is thedominating factor among interconnect variations. Experimental resultson benchmark circuits show that this bound is safer, tighterand computationally faster than similar existing approach.

References

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Cited By

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  • (2005)Clock skew bounds estimation under power supply and process variationsProceedings of the 15th ACM Great Lakes symposium on VLSI10.1145/1057661.1057741(332-336)Online publication date: 17-Apr-2005

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cover image ACM Conferences
ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
November 2003
899 pages
ISBN:1581137621

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IEEE Computer Society

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Publication History

Published: 09 November 2003

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ICCAD '03 Paper Acceptance Rate 129 of 490 submissions, 26%;
Overall Acceptance Rate 457 of 1,762 submissions, 26%

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  • (2005)Clock skew bounds estimation under power supply and process variationsProceedings of the 15th ACM Great Lakes symposium on VLSI10.1145/1057661.1057741(332-336)Online publication date: 17-Apr-2005

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